Emulator Cable Pod Signal Timing
E-6
E.4 Emulator Cable Pod Signal Timing
Figure E–3 shows the signal timings for the emulator cable pod. Table E–2
defines the timing parameters illustrated in the figure. These timing parame-
ters are calculated from values specified in the standard data sheets for the
emulator and cable pod and are for reference only. Texas Instruments does
not test or guarantee these timings.
The emulator pod uses TCK_RET as its clock source for internal synchroni-
zation. TCK is provided as an optional target system test clock source.
Figure E–3. Emulator Cable Pod Timings
TDO
TMS, TDI
TCK_RET
6
5
4
3
2
1
Table E–2. Emulator Cable Pod Timing Parameters
No.
Parameter
Description
Min
Max
Unit
1
t
c(TCK)
Cycle time, TCK_RET
35
200
ns
2
t
w(TCKH)
Pulse duration, TCK_RET high
15
ns
3
t
w(TCKL)
Pulse duration, TCK_RET low
15
ns
4
t
d(TMS)
Delay time, TMS or TDI valid for TCK_RET low
6
20
ns
5
t
su(TDO)
Setup time, TDO to TCK_RET high
3
ns
6
t
h(TDO)
Hold time, TDO from TCK_RET high
12
ns
