F-15
Glossary
MSTACK:
See
micro stack.
multiplier:
A part of the CPU that performs 16-bit
×
16-bit multiplication and
generates a 32-bit product. The multiplier operates using either signed
or unsigned 2s-complement arithmetic.
N
next AR:
See
next auxiliary register.
next auxiliary register:
The register that will be pointed to by the auxiliary
register pointer (ARP) when an instruction that modifies ARP is finished
executing. See also
auxiliary register; current auxiliary register.
NMI:
A hardware interrupt that uses the same logic as the maskable inter-
rupts but cannot be masked. It is often used as a soft reset. See also
maskable interrupt; nonmaskable interrupt.
nonmaskable interrupt:
An interrupt that can be neither masked by the in-
terrupt mask register (IMR) nor disabled by the INTM bit of status register
ST0.
NPAR:
Next program address register. Part of the program-address genera-
tion logic. This register provides the address of the next instruction to the
program counter (PC), the program address register (PAR), the micro
stack (MSTACK), or the stack.
O
OE:
Receiver register overrun indicator bit. Bit 9 of the I/O status register
(IOSR); indicates whether overrun has occurred in the receiver of the
asynchronous serial port (that is, whether an unread character in the
ADTR has been overwritten by a new character).
operand:
A value to be used or manipulated by an instruction; specified in
the instruction.
operand-fetch phase:
The third phase of the pipeline; the phase in which
an operand or operands are fetched from memory. See also
pipeline;
instruction-fetch phase; instruction-decode phase; instruction-execute
phase.
output shifter:
32- to 16-bit barrel left shifter. Shifts the 32-bit accumulator
output from 0 to 7 bits left for quantization management, and outputs ei-
ther the 16-bit high or low half of the shifted 32-bit data to the data write
bus (DWEB).
Glossary
