SPRA921
7
TMS320C6713 Digital Signal Processor Optimized for High Performance Multichannel Audio Systems
3.3
Unified L2 for Program and Data
By unifying the program and data in the L2 space, the L2 cache is more likely to hold the
memory requested by the CPU. It enables the on-chip memory to contain more data than
program when highly computational, looping code is being run to process large data streams.
For long, serial code with few data accesses, the L2 may be more densely populated with
program instructions. The unification allows you to allocate the appropriate amount of memory
for both program and data and keeps the on-chip memory full of instructions and data that are
the most likely to be requested by the CPU.
3.4
Real Time Features
An important concern in audio systems is that the device be able to perform in real time. There
are several requirements for a system to ensure that real-time operation is possible. The
operation of the device must be predictable, interrupts to the CPU must be handled without
affecting the continued real-time operation of the device, and efficient I/O must be maintained.
3.4.1
Interrupt Handling
Interrupt handling is an important part of DSP operation. It is crucial that the DSP be able to
receive and handle interrupts while maintaining real-time operation. In typical applications,
interrupt frequency has not increased in proportion to the increase in device operation
frequency. As processing speeds have increased, latency requirements have not.
The TMS320C6713 is capable of servicing interrupts with a latency of a fraction of a
microsecond when the service routine is located in external memory. By configuring the L2
memory blocks as memory-mapped SRAM, or by using the L2 memory mapped space, it is
possible to lock critical program and data sections into internal memory. This is ideal for
situations such as interrupts and OS task switching. By locking routines that need to be
performed in minimal time, the microsecond delay for interrupts is reduced to tens of
nanoseconds.
3.4.2
Real Time I/O
Peripherals are a feature of most DSP systems that can take advantage of the memory-mapped
L2 RAM. Typical processors require that peripheral data first be placed in external memory
before it can be accessed by the CPU. The TMS320C6713 can maintain data buffers in on-chip
memory, rather than in off-chip memory, providing a higher data throughput to peripherals. This
increases performance when using on-chip McASPs, the HPI, or external peripherals. The
EDMA can be used to transfer data directly into mapped L2 space while the CPU processes the
data. This increases performance since the CPU is not stalled while fetching data from slow
external memory or directly from the peripheral. Using this method for transferring data also
minimizes EMIF activity, which is crucial as data rates or the number of peripherals increase.
