www.ti.com
5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)
SRIO Registers
The bits in this register indicate any active interrupt requests from TX buffer descriptor queues.
TX_CPPI_ICSR is shown in
Figure 81
and described in
Table 71
.
Figure 81. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) - Address Offset 0250h
31
16
Reserved
R-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ICS15
ICS14
ICS13
ICS12
ICS11
ICS10
ICS9
ICS8
ICS7
ICS6
ICS5
ICS4
ICS3
ICS2
ICS1
ICS0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = Value after reset
Table 71. TX CPPI Interrupt Condition Status Register (TX_CPPI_ICSR) Field Descriptions
Bit
Field
Value
Description
31–16
Reserved
0
These read-only bits return 0 when read.
15–0
ICSx
TX CPPI interrupt status
(x = 15 to 0)
0
TX buffer descriptor queue x has not generated an interrupt request.
1
TX buffer descriptor queue x has generated an interrupt request.
Serial RapidIO (SRIO)
136
SPRUE13A – September 2006
Submit Documentation Feedback
