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2.3.2.4
SERDES Configuration Example
2.3.3
Direct I/O Operation
SRIO Functional Description
Table 13. SWING Bits of SERDES_CFGTXn_CNTL
SWING Bits
Amplitude (mV
dfpp
)
000b
125
001b
250
010b
500
011b
625
100b
750
101b
1000
110b
1125
111b
1250
//full sample rate at 3.125 Gbps
//SERDES reference clock (RIOCLK) 125 MHz
//MPY = 12.5
125MHz = ((3.125 Gbps)(.5))/MPY
SRIO_REGS->SERDES_CFG0_CNTL = 0x0000000F;
SRIO_REGS->SERDES_CFG1_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG2_CNTL = 0x00000000;
SRIO_REGS->SERDES_CFG3_CNTL = 0x00000000;
// SRIO_REGS->SERDES_CFG1_CNTL not used
// SRIO_REGS->SERDES_CFG2_CNTL not used
// SRIO_REGS->SERDES_CFG3_CNTL not used
//four ports enabled
SRIO_REGS->SERDES_CFGRX0_CNTL
= 0x00081101 ;
SRIO_REGS->SERDES_CFGRX1_CNTL
= 0x00081101 ;
SRIO_REGS->SERDES_CFGRX2_CNTL
= 0x00081101 ;
SRIO_REGS->SERDES_CFGRX3_CNTL
= 0x00081101 ;
SRIO_REGS->SERDES_CFGTX0_CNTL
= 0x00010801 ;
SRIO_REGS->SERDES_CFGTX1_CNTL
= 0x00010801 ;
SRIO_REGS->SERDES_CFGTX2_CNTL
= 0x00010801 ;
SRIO_REGS->SERDES_CFGTX3_CNTL
= 0x00010801 ;
The direct I/O (Load/Store) module serves as the source of all outgoing direct I/O packets. With direct I/O,
the RapidIO packet contains the specific address where the data should be stored or read in the
destination device. Direct I/O requires that a RapidIO source device keep a local table of addresses for
memory within the destination device. Once these tables are established, the RapidIO source controller
uses this data to compute the destination address and insert it into the packet header. The RapidIO
destination peripheral extracts the destination address from the received packet header and transfers the
payload to memory via the DMA.
When a CPU wants to send data from memory to an external processing element (PE) or read data from
an external PE, it provides the RIO peripheral vital information about the transfer such as DSP memory
address, target device ID, target destination address, packet priority, etc. Essentially, a means must exist
to fill all the header fields of the RapidIO packet. The Load/Store module provides a mechanism to handle
this information exchange via a set of MMRs acting as transfer descriptors. These registers, shown in
Figure 12
, are addressable by the CPU through the configuration bus. Upon completion of a write to
LSUn_REG5, a data transfer is initiated for either an NREAD, NWRITE, NWRITE_R, SWRITE, ATOMIC,
or MAINTENANCE RapidIO transaction. Some fields, such as the RapidIO srcTID/targetTID field, are
assigned by hardware and do not have a corresponding command register field.
SPRUE13A – September 2006
Serial RapidIO (SRIO)
35
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