www.ti.com
2.3.3.4
Reset and Power Down State
2.3.4
Message Passing
SRIO Functional Description
So the general flow is as follows:
•
Previously, the control/command registers were written and the request packet was sent
•
Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not
based on priority)
•
The argetTID is examined to determine routing of a response to the appropriate core
•
The status field of the response packet is checked for ERROR, RETRY or DONE
•
If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address. If
the field is ERROR/RETRY, it sets an interrupt
•
Command registers are released (BSY = 0)
•
Optional Interrupt to CPU notifying packet reception
Upon reset, the Load/Store module clears the command register fields and wait for a write by the CPU.
The Load/Store module can be powered down if the direct I/O protocol is not being supported in the
application. For example, if the messaging protocol is being used for data transfers, powering down the
Load/Store module will save power. In this situation, the command registers should be powered down and
inaccessible. Clocks should be gated to these blocks while in the power down state.
The Communications Port Programming Interface (CPPI) module is the incoming and outgoing
message-passing protocol engine of the RapidIO peripheral. Messages contain application specific data
that is pushed to the receiving device comparable to a streaming write. Messages do not contain read
operations, but do have response packets.
With message passing, a destination address is not specified. Instead, a mailbox identifier is used within
the RapidIO packet. The mailbox is controlled and mapped to memory by the local (destination) device.
For RapidIO message passing, four mailbox locations are specified. Each mailbox can contain 4 separate
transactions (or letters), effectively providing 16 messages. Single packet messages provide 64 mailboxes
with 4 letters, effectively providing 256 messages. Mailboxes can be defined for different data types or
priorities. The advantage of message passing is that the source device does not require any knowledge of
the destination device’s memory map. The DSP contains buffer description tables for each mailbox. These
tables define a memory map and pointers for each mailbox. Messages are transferred to the appropriate
memory locations via the DMA.
The data path for this module uses the DMA bus as the DMA interface. The ftype header field of the
received RapidIO message packets are decoded by the logical layer of the peripheral. Only Type 11 and
Type 13 (transaction type 1) packets are routed to this module. Data is routed from the priority-based RX
FIFOs to the CPPI module’s data buffer within the shared buffer pool. The mbox (mailbox) header fields
are examined by the mailbox mapper block of the CPPI module. Based on the mailbox and message
length, the data is assigned memory addresses within memory. Data is transferred via DMA bus
commands to memory from the buffer space of the peripheral. The maximum buffer space should
accommodate 256 bytes of data, as that is the maximum payload size of a RapidIO packet. Each
message in memory will be represented by a buffer descriptor in the queue.
The following rules exist for all CPPI traffic:
•
One buffer descriptor is provided per message (each buffer descriptor consists of 4 words or 16 bytes).
•
Contiguous memory space is required for multi-segment read and write operations.
–
There are fixed buffer sizes (configured to handle the application's maximum message size).
•
An ERROR response is sent if the RX message is too big for the allotted buffer space.
–
ERROR responses are sent for all subsequent segments of that message.
•
An ERROR response is sent if the mailbox is not mapped, or if it is mapped to a non-existent queue.
•
An ERROR response is sent if the mailbox is mapped but the queue is not initialized (the head
descriptor pointer is not written), or if the queue is disabled (due to a teardown).
•
An ERROR response is sent if the RX buffer descriptor queue has no empty buffers (there is an
overflow) .
SPRUE13A – September 2006
Serial RapidIO (SRIO)
43
Submit Documentation Feedback
