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4.3
Interrupt Condition Status and Clear Registers
Interrupt Conditions
The DOORBELL packet’s 16-bit INFO field indicates which DOORBELL register interrupt bit to set. There
are four DOORBELL registers, each currently with 16 bits, allowing 64 interrupt sources or circular buffers
(see
Table 23
for assignment of the 16 bits of DOORBELL_INFO field). Each bit can be assigned to any
core as described by the Interrupt Condition Routing Registers. Additionally, each status bit is
user-defined for the application. For instance, it may be desirable to support multiple priorities with multiple
TID circular buffers per core if control data uses a high priority (for example, priority = 2), while data
packets are sent on priority 0 or 1. This allows the control packets to have preference in the switch fabric
and arrive as quickly as possible. Since it may be required to interrupt the CPU for both data and control
packet processing separately, separate circular buffers are used, and DOORBELL packets must
distinguish between them for interrupt servicing. If any reserved bit in the DOORBELL info field is set, an
error response is sent.
The interrupt approach to the messaging protocol is somewhat different. Since the source device is
unaware of the data's physical location in the destination device, and since each messaging packet
contains size and segment information, the peripheral can automatically generate the interrupt after it has
successfully received all packet segments comprising the complete message. This DMA interface uses
the Communications Port Programming Interface (CPPI). This interface is a link-listed approach versus a
circular buffer approach. Data buffer descriptors which contain information such as start of Packet (SOP),
end of packet (EOP), end of queue (EOQ), and packet length are built from the RapidIO header fields.
The data buffer descriptors also contain the address of the corresponding data buffer as assigned by the
receive device. The data buffer descriptors are then link-listed together as multiple packets are received.
Interrupts are generated by the peripheral after all segments of the messages are received and
successfully transferred through the DMA bus with the write-with-response commands. Interrupt pacing is
also implemented at the peripheral level to manage the interrupt rate, as described in
Section 4.7
.
Error handling on the RapidIO link is handled by the peripheral, and as such, does not require the
intervention of software for recovery. This includes CRC errors due to bit rate errors that may cause
erroneous or invalid operations. The exception to this statement is the use of the RapidIO error
management extended features. This specification monitors and tabulates the errors that occur on a per
port basis. If the number of errors exceeds a pre-determined configurable amount, the peripheral should
interrupt the CPU software and notify that an error condition exits. Alternatively, if a system host is used,
the peripheral may issue a port-write operation to notify the system software of a bad link.
A system reset, or Critical Error interrupt, can be initialized through the RapidIO link. This procedure
allows an external device to reset the local device, causing all state machine and configuration registers to
reset to their original values. This is executed with the Reset-Device command described in Part VI,
Section 3.4.5 of the RapidIO Physical Layer 1x/4x LP-Serial Specification. Four sequential Reset-Device
control symbols are needed to avoid inadvertent resetting of a device.
Interrupt condition status and clear registers configure which CPU interrupts are to be generated and how,
based on the peripheral activity. All peripheral conditions that result in a CPU interrupt are grouped so that
the interrupt can be accessed in the minimum number of register reads possible.
For each of the three types of interrupts (CPU servicing, error status, and critical error), there are two sets
of registers:
•
Interrupt Condition Status Register (ICSR): Status register that reflects the state of each condition that
can trigger the interrupt. The general description of each interrupt condition status bit (ICSx) is given in
Table 35
.
•
Interrupt Condition Clear Register (ICCR): Command register that allows each condition to be cleared.
This is typically required prior to enabling a condition, so that spurious interrupts are not generated.
Table 35
shows the general description of an interrupt condition clear bit (ICCx).
These registers are accessible in the memory map of the CPU. The CPU controls the clear register. The
status register is readable by the CPU to determine the peripheral condition.
Serial RapidIO (SRIO)
86
SPRUE13A – September 2006
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