19
SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016
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Copyright © 2016, Texas Instruments Incorporated
7.18 Analog-to-Digital Converter (ADC) Characteristics
Recommended operating conditions; T
A
= –40°C to +105°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RES_ADC
ADC current
10
bits
F_ADC
ADC clock frequency
1.477
1.5
1.523
MHz
T_ENA
ADC enable time
42.14
43
43.86
μ
s
T_SAMPLEA
ADC input sample time
10.5
10.67
10.9
μ
s
T_CONVERTA
ADC conversion time
7.88
8
8.12
μ
s
T_INTA
ADC interrupt time
1.31
1.33
1.45
μ
s
LSB
Least significant bit
1.152
1.17
1.188
mV
DNL
Differential non-linearity
–0.65
0.65
LSB
INL
Integral non-linearity
–1.2
1.2
LSB
GAIN_ERR
Gain error (divider)
–1.5%
1.5%
Gain error (no divider)
–1
1
VOS_ERR
Buffer offset error
–10
10
mV
THERM_ACC
Thermal sense accuracy
–8
8
°C
THERM_GAIN
Thermal slope
3.095
mV/°C
THERM_V0
Zero degree voltage
0.823
V
7.19 Input-Output (I/O) Requirements and Characteristics
Recommended operating conditions; T
A
= –40°C to +105°C unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPI
SPI_VIH
High-level input voltage
LDO_3V3 = 3.3 V
2
V
SPI_VIL
Low-level input voltage
LDO_3V3 = 3.3 V
0.8
V
SPI_HYS
Input hysteresis voltage
LDO_3V3 = 3.3 V
0.2
V
SPI_ILKG
Leakage current
Output is Hi-Z, V
IN
= 0 to LDO_3V3
–1
1
μ
A
SPI_VOH
SPI output-high voltage
I
O
= –8 mA, LDO_3V3=3.3 V
2.9
V
I
O
= –15 mA, LDO_3V3=3.3 V
2.5
SPI_VOL
SPI output-low voltage
I
O
= 10 mA
0.4
V
I
O
= 20 mA
0.8
SWDIO
SWDIO_VIH
High-level input voltage
LDO_3V3 = 3.3 V
2
V
SWDIO_VIL
Low-level input voltage
LDO_3V3 = 3.3 V
0.8
V
SWDIO_HYS
Input hysteresis voltage
LDO_3V3 = 3.3 V
0.2
V
SWDIO_ILKG
Leakage current
Output is Hi-Z, V
IN
= 0 to LDO_3V3
–1
1
μ
A
SWDIO_VOH
Output high voltage
I
O
= –8 mA, LDO_3V3 = 3.3 V
2.9
V
I
O
= –15 mA, LDO_3V3 = 3.3 V
2.5
SWDIO_VOL
Output low voltage
I
O
= 10 mA
0.4
V
I
O
= 20 mA
0.8
SWDIO_RPU
Pull-up resistance
2.8
4
5.2
k
Ω
SWDIO_TOS
SWDIO output skew to falling edge SWDCLK
–5
5
ns
SWDIO_TIS
Input setup time required between SWDIO and rising
edge of SWCLK
6
ns
SWDIO_TIH
Input hold time required between SWDIO and rising edge
of SWCLK
1
ns
SWDCLK
SWDCL_VIH
High-level input voltage
LDO_3V3 = 3.3 V
2
V
SWDCL_VIL
Low-level input voltage
LDO_3V3 = 3.3 V
0.8
V
SWDCL_THI
SWDIOCLK HIGH period
0.05
500
μ
s
SWDCL_TLO
SWDIOCLK LOW period
0.05
500
μ
s
SWDCL_HYS
Input hysteresis voltage
LDO_3V3 = 3.3 V
0.2
V
