Data Line
Change
SDA
SCL
P
S
Start Condition
Stop Condition
SDA
SCL
71
SLVSDC2B – FEBRUARY 2016 – REVISED AUGUST 2016
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Copyright © 2016, Texas Instruments Incorporated
Programming (continued)
9.5.2.1 I
2
C Interface Description
The TPS65981 support Standard and Fast mode I
2
C interface. The bi-directional I
2
C bus consists of the serial
clock (SCL) and serial data (SDA) lines. Both lines must be connected to a supply through a pull-up resistor.
Data transfer may be initiated only when the bus is not busy.
A master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high
initiates I
2
C communication. After the Start condition, the device address byte is sent, most significant bit (MSB)
first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. On the I
2
C bus, only one data bit is transferred
during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period
as changes in the data line at this time are interpreted as control commands (Start or Stop). The master sends a
Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high.
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period. When a
slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must
generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to
ensure proper operation
A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. The master receiver holding the SDA line high does this. In this
event, the transmitter must release the data line to enable the master to generate a stop condition.
shows the start and stop conditions of the transfer.
shows the SDA and SCL signals for
transferring a bit.
shows a data transfer sequence with the ACK or NACK at the last clock pulse.
Figure 67. I
2
C Definition of Start and Stop Conditions
Figure 68. I
2
C Bit Transfer
