SLOU186F
–
AUGUST 2006
–
REVISED AUGUST 2010
The main register controlling the digital part of the receiver is the ISO control register (address 01). By
writing to this register, the user selects the protocol to be used. With each new write in this register, the
default presets are loaded in all related registers, so no further adjustments in other registers are needed
for proper operation.
shows the coding of the ISO control register. Note that the TRF7961 does not include the
ISO14443 functionality; its features/commands in this area are non-functional.
The framing section also supports the bit-collision detection as specified in ISO14443A. When a bit
collision is detected, an interrupt request is sent and flag set in the IRQ and status register. The position of
the bit collision is written in two registers. Register collision position, with address 0E, and in register
collision position and interrupt mask (address 0D), in which only the bits B7 and B6 are used for collision
position. The collision position is presented as a sequential bit number, where the count starts immediately
after the start bit. For example, the collision in the first bit of the UID would give the value 00 0001 0000 in
the collision-position registers. The count starts with 0, and the first 16 bits are the command code and the
NVB byte. Note: the NVB byte is the number of valid bits.
The receive section also has two timers. The RX-wait-time timer is controlled by the value in the RX wait
time register (address 08). This timer defines the time after the end of the transmit operation in which the
receive decoders are not active (held in reset state). This prevents incorrect detections resulting from
transients following the transmit operation. The value of the RX wait time register defines this time in
increments of 9.44
μ
s. This register is preset at every write to ISO control register (address 01) according
to the minimum tag-response time defined by each standard.
The RX no-response timer is controlled by the RX no response wait time register (address 07). This timer
measures the time from the start of slot in the anti-collision sequence until the start of tag response. If
there is no tag response in the defined time, an interrupt request is sent and a flag is set in IRQ status
control register. This enables the external controller to be relieved of the task of detecting empty slots. The
wait time is stored in the register in increments of 37.76
μ
s. This register is also preset, automatically, for
every new protocol selection.
5.2.3
Transmitter
The transmitter section consists of the 13.56-MHz oscillator, digital protocol processing, and RF output
stage.
5.2.3.1
Transmitter
–
Analog
The 13.56-MHz crystal oscillator (connected to pins 31 and 32) directly generates the RF frequency for the
RF output stage. Additionally, it also generates the clock signal for the digital section and clock signal
displayed for the SYS_CLK (pin 27) which can be used by an external MCU system.
During partial power-down mode (EN = 0, EN2 = 1), the frequency of SYS_CLK is 60 kHz. During normal
reader operation, SYS_CLK can be programmed by bits B4 and B5 in the modulator and SYS_CLK
control register (address 09); available clock frequencies are 13.56 MHz, 6.78 MHz, or 3.39 MHz.
The reference crystal (HC49U) should have the following characteristics:
Parameter
Specification
Frequency
13.560000 MHz
Mode of operation
Fundamental
Type of resonance
Parallel
Frequency tolerance
±
20 ppm
Aging
<
5 ppm/year
Operation temperature range
–
40
°
C to 85
°
C
Equivalent series resistance
50
Ω
, minimum
Copyright
©
2006
–
2010, Texas Instruments Incorporated
System Description
19
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