Texas Instruments TRF7960, Manual

Page 1: ...ault Modes for Each Supported ISO Protocol 12 User Programmable Registers Selectable Receiver Gain and AGC Programmable Output Power 100 mW or 200 mW Adjustable ASK Modulation Range 8 to 30 Built In Receiver Band Pass Filter With User Selectable Corner Frequencies Wide Operating Voltage Range of 2 7 V to 5 5 V Ultra Low Power Modes Power Down 1 μA Standby 120 μA Active Rx only 10 mA 1 3 Descriptio...

Page 2: ...m Table 1 1 PRODUCT SELECTION TABLE PROTOCOLS DEVICE ISO14443A B ISO15693 Tag it ISO18000 3 106 kbps 212 kbps 424 kbps 848 kbps TRF7960 TRF7961 2 Introduction Copyright 2006 2010 Texas Instruments Incorporated Submit Documentation Feedback focus ti com TRF7960 TRF7961 ...

Page 3: ...lies 11 3 1 Terminal Functions 5 5 2 Receiver Analog Section 17 5 3 Register Descriptions 24 3 2 PACKAGING ORDERING INFORMATION 6 5 4 Direct Commands From MCU to Reader 34 4 ELECTRICAL SPECIFICATIONS 7 5 5 Reader Communication Interface 36 4 1 ABSOLUTE MAXIMUM RATINGS 7 5 6 Parallel Interface Communication 38 4 2 DISSIPATION RATINGS TABLE 7 5 7 Serial Interface Communication 40 4 3 RECOMMENDED OPE...

Page 4: ...n of SOF EOF CRC and or parity bits The receiver system enables AM and PM demodulation using a dual input architecture The receiver also includes an automatic gain control option and selectable gain Also included is a selectable bandwidth to cover a broad range of input sub carrier signal options The received signal strength for AM and PM modulation is accessible via the RSSI register The receiver...

Page 5: ... substrate ground BAND_GAP 11 OUT Band gap voltage 1 6 V internal analog voltage reference must be ac bypassed to ground Also can be configured to provide the received analog signal output ANA_OUT ASK OOK 12 BID Direct mode selection between ASK and OOK modulation 0 ASK 1 OOK IRQ 13 OUT Interrupt request MOD 14 INP Direct mode external modulation input VSS_A 15 SUP Negative supply for internal ana...

Page 6: ...and EN2 1 then system clock is set to 60 kHz EN 28 INP Chip enable input If EN 0 then chip is in power down mode VSS_D 29 SUP Negative supply for internal digital circuits normally connected to circuit ground OSC_OUT 30 OUT Crystal oscillator output OSC_IN 31 INP Crystal oscillator input VDD_X 32 OUT Internally regulated supply 2 7 V 3 4 V for external circuitry MCU Thermal Pad Connected to circui...

Page 7: ...operation of the device at these or any other conditions beyond those specified are not implied 2 The maximum junction temperature for continuous operation is limited by package constraints Operation above this temperature may result in reduced reliability and or lifetime of the device 4 2 DISSIPATION RATINGS TABLE POWER RATING 2 θJC θJA 1 PACKAGE C W C W TA 25 C TA 85 C RHB 32 31 36 4 2 7 W 1 1 W...

Page 8: ...ulated supply for RF circuitry Regulator set for 5 V system with 250 mV difference 4 6 V 5 2 MAX 3 1 MIN VDD_X Regulated supply for external circuitry 3 4 V 3 8 MAX The difference between the external supply and the Rejection of external supply noise on PPSRR regulated voltage is higher than 250 mV Measured at 26 20 dB MIN the supply VDD_RF regulator 212 kHz Half power mode 8 12 Ω MAX RRFOUT PA dr...

Page 9: ...F 2 2 uF 10 nF 10 nF 10 nF 10 nF 2 2 uF 2 2 uF 2 2 uF 0 Ohms 0 Ohms 27 pF 27 pF 13 56 MHz VSWR Adj DVcc D AVss XIN 1 K 1 K Reader Pwr Enable GPIO Interrupt Capable GPIO MSP430 Family 4 7 uF 10V 0 1 uF 1 K CLK GPIO PX 7 PX 6 PX 5 PX 4 PX 3 PX 2 PX 1 PX 0 Vcc 100 0 1 uF 2 2 uF 10 nF 10K 10 pF Harmonic Suppression C1 C2 Xtal C L C S C1 C2 Antenna Circuit Ant Q Adj R cal open short load TRF7960 TRF796...

Page 10: ...2 F µ 10 nF 10 nF 10 nF 10 nF 2 2 F µ 2 2 F µ 2 2 F µ 0 Ohms 0 Ohms 27 pF 27 pF 13 56 MHz VSWR Adj Vcc DVcc D AVss MISO MOSI XIN 10 K 10 K 1 K 1 K CLK GPIO Slave Select GPIO Reader Pwr Enable GPIO Interrupt Capable GPIO MSP430 Family 4 7 F 10V µ 0 1 F µ 1 K 100 0 1 F µ 2 2 F µ 10 nF 10 pF Harmonic Suppression 10 K C1 C2 Xtal C L C S C1 C2 Antenna Circuit Ant Q Adj R cal open short load TRF7960 TRF...

Page 11: ...r 3 V operation the output can be set from 2 7 V to 3 4 V in 100 mV steps Note that when configured both VDD_A and VDD_X regulators are configured together their settings are not independent VDD_X Regulator VDD_X pin 32 can be used to source the digital I O of the reader chip together with other external system components When configured for 5 V operation the output voltage is fixed at 3 4 V When ...

Page 12: ...improve the PSRR if there is a noisy supply voltage from VDD_X by increasing the target voltage difference across the VDD_X regulator as shown for automatic regulator settings in Table 5 3 and Table 5 4 Table 5 1 Supply Regulator Setting Manual 5 V System Byte Option Bits Setting in Control Register Action Address B7 B6 B5 B4 B3 B2 B1 B0 00 1 5 V system 0B 0 Manual regulator setting 0B 0 1 1 1 VDD...

Page 13: ...availability of the regulated supply VDD_X and an auxiliary clock signal 60 kHz on the SYS_CLK output same for the case EN 0 This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator VDD_X and the MCU clock is supplied by the SYS_CLK output of the reader This allows the MCU supply and clock to be available during power down A se...

Page 14: ...ed supply VDD_X and auxiliary clock 60 kHz SYS_CLK are available to the MCU or other system device When EN is set high or on rising edge of EN2 and then confirmed by EN 1 the supply regulators are activated and the 13 56 MHz oscillator started When the supplies are settled and the oscillator frequency is stable the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the selected f...

Page 15: ...CHIP POWER UP TO CLOCK START Figure 5 1 Power Up VIN Blue to Crystal Start Red CHIP ENABLE TO CLOCK START Figure 5 2 EN2 Low and EN High Blue to Start of System Clock Red Copyright 2006 2010 Texas Instruments Incorporated System Description 15 Submit Documentation Feedback focus ti com TRF7960 TRF7961 ...

Page 16: ...ED AUGUST 2010 www ti com CHIP ENABLE TO CLOCK START Figure 5 3 EN2 High and EN Low Blue to Start of System Clock Red 16 System Description Copyright 2006 2010 Texas Instruments Incorporated Submit Documentation Feedback focus ti com TRF7960 TRF7961 ...

Page 17: ...ndpass filter The bandpass filter has adjustable 3 dB frequency steps 100 kHz to 400 kHz for high pass and 600 kHz to 1500 kHz for low pass Following the bandpass filter is another gain and filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first stage The internal filters are configured automatically with internal presets for each new selection of a co...

Page 18: ...section consists of framing logic The bit decoders convert the sub carrier coded signal to a bit stream and also to the data clock Thus the sub carrier coded signal is transformed to serial data and the data clock is extracted The decoder logic is designed for maximum error tolerance This enables the decoders to successfully decode even partly corrupted due to noise or interference sub carrier sig...

Page 19: ...ation The value of the RX wait time register defines this time in increments of 9 44 μs This register is preset at every write to ISO control register address 01 according to the minimum tag response time defined by each standard The RX no response timer is controlled by the RX no response wait time register address 07 This timer measures the time from the start of slot in the anti collision seque...

Page 20: ...ange of the ASK modulation is 7 30 or 100 OOK The coding of the modulator and SYS_CLK control register is shown in Table 5 19 The length of the modulation pulse is defined by the protocol selected in the ISO control register With a high Q antenna the modulation pulse is typically prolonged and the tag detects a longer pulse than intended For such cases the modulation pulse length can be corrected ...

Page 21: ...is entered into the ISO control register Some protocols have options two registers are provided to select the TX protocol options The first such register is ISO14443B TX options address 02 It controls the SOF and EOF selection and EGT extra guard time selection for the ISO14443B protocol The bit definitions of this register are given in Table 5 12 The second register controls the ISO14443 high bit...

Page 22: ...e the user must first choose which direct mode to enter by writing B6 in the ISO control register This bit determines if the receive output is the direct sub carrier signal B6 0 or the serial data of the selected decoder If B6 1 then the user must also define which protocol should be used for bit decoding by writing the appropriate setting in the ISO control register The reader actually enters the...

Page 23: ...t the circuitry optimally to the appropriate protocol parameters When entering another protocol writing to the ISO control register 01 the low level option registers 02 0B are automatically configured to the new protocol parameters After selecting the protocol it is possible to change some low level register contents if needed However changing to another protocol and then back reloads the default ...

Page 24: ...length control R W 07 RX no response wait R W 08 RX wait time R W 09 Modulator and SYS_CLK control R W 0A RX special setting R W 0B Regulator and I O control R W 16 Unused NA 17 Unused NA 18 Unused NA 19 Unused NA Status Registers 0C IRQ status R 0D Collision position and interrupt mask register R W 0E Collision position R 0F RSSI levels and oscillator status R FIFO Registers 1C FIFO status R 1D T...

Page 25: ...l is on I 0_6 0 received decoded signal from selected decoder B5 rf_on 1 RF output active When B5 1 it activates the RF field 0 RF output not active B4 rf_pwr 1 half output power 1 RF driver at 8 Ω 0 full output power 0 RF driver at 4 Ω B3 pm_on 1 RX_IN2 1 Selects PM signal input 0 RX_IN1 0 Selects AM signal input B2 agc_on 1 AGC on AGC selection 0 AGC off B1 rec_on 1 Reciever enable for external ...

Page 26: ...rate 26 48 kbps one sub carrier 1 out of 4 Default for reader 0 0 0 1 1 ISO15693 high bit rate 26 48 kbps one sub carrier 1 out of 256 0 0 1 0 0 ISO15693 low bit rate 6 67 kbps double sub carrier 1 out of 4 0 0 1 0 1 ISO15693 low bit rate 6 67 kbps double sub carrier 1 out of 256 0 0 1 1 0 ISO15693 high bit rate 26 69 kbps double sub carrier 1 out of 4 0 0 1 1 1 ISO15693 high bit rate 26 69 kbps d...

Page 27: ...s B7 dif_tx_br TX bit rate different than RX bit rate enable Valid for ISO14443A B high bit rate B6 tx_br1 TX bit rate tx_br1 0 tx_br 0 106 kbps tx_br1 0 tx_br 1 212 kbps B5 tx_br0 tx_br1 1 tx_br 0 424 kbps tx_br1 1 tx_br 1 848 kbps B4 parity 2tx 1 parity odd except last byte which is even for TX For 14443A high bit rate coding and decoding B3 parity 2rx 1 parity odd except last byte which is even...

Page 28: ...ze 73 7 ns All bits low 00 pulse length control is disabled B6 Pul_p1 Preset 9 44 μs ISO15693 B5 Pul_p0 Preset 11 μs Tag It Preset 2 36 μs ISO14443A B4 Pul_c4 Preset 1 4 μs ISO14443A at 212 kbps B3 Pul_c3 Preset 737 ns ISO14443A at 424 kbps Preset 442 ns ISO14443A at 848 kbps pulse length control is disabled B2 Pul_c2 B1 Pul_c1 B0 Pul_c0 Pulse length LSB Table 5 17 RX No Response Wait Time 07h Def...

Page 29: ...ontrol Register default is set to 0x11 at POR H or EN L and at each write to ISO control register except Clo1 and Clo0 Bit Bit Name Function Comments B7 Unused B6 en_ook_p 1 enables external selection of ASK or OOK Valid only when ISO control register 01 is configured to direct mode modulation B5 Clo1 SYS_CLK output frequency MSB Clo1 Clo0 CL_SYS Output state B4 Clo0 SYS_CLK output frequency LSB 0...

Page 30: ...he digitizing level B0 no lim AGC action is not limited in time AGC action can be done any time during receive process It is not limited to the start of receive Table 5 21 Regulator and I O Control 0Bh Control the three voltage regulators Register default is set to 0x87 at POR H or EN L Bit Bit Name Function Comments B7 auto_reg 0 setting regulator by option bits Auto system sets VDD_RF to VIN 250...

Page 31: ...ponse interrupt Signal to MCU that next slot command can be sent Table 5 23 Collision Position and Interrupt Mask Register 0Dh Register default is set to 3E at POR H and EN L Collision bits reset automatically after read operation Bit Bit Name Function Comments B7 Col9 Bit position of collision MSB Supported ISO15693 single sub carrier and ISO14443A B6 Col8 Bit position of collision B5 En_irq_fifo...

Page 32: ...5 rssi_x2 RSSI value of auxiliary channel 4 dB Auxiliary channel is by default PM It can be set to AM with B3 of chip state per step MSB control register 00 B4 rssi_x1 B3 rssi_x0 RSSI value of auxiliary channel 4 dB per step LSB B2 rssi_2 RSSI value of active channel 4 dB Active channel is default AM and can be set to PM with option bit B3 of chip per step MSB state control register 00 B1 rssi_1 B...

Page 33: ...complete bytes to be transmitted B6 Txl10 Number of complete byte bn 10 B5 Txl9 Number of complete byte bn 9 B4 Txl8 Number of complete byte bn 8 B3 Txl7 Number of complete byte bn 7 Middle nibble of complete bytes to be transmitted B2 Txl6 Number of complete byte bn 6 B1 Txl5 Number of complete byte bn 5 B0 Txl4 Number of complete byte bn 4 Table 5 28 TX Length Byte2 1Eh Low nibbles of complete b...

Page 34: ...ears the register storing the collision error location 0Eh 5 4 3 Transmission With CRC The transmission command must be sent first followed by transmission length bytes and FIFO data The reader starts transmitting after the first byte is loaded into the FIFO The CRC byte is included in the transmitted sequence 5 4 4 Transmission Without CRC Same as Section 5 4 3 with CRC excluded 5 4 5 Delayed Tra...

Page 35: ...nd enable RX 5 4 10 Test Internal RF RSSI at RX input with TX ON This command measures the level of the RF carrier at the receive inputs Its operating range is between 300 mVp and 2 1 Vp with a step size of 300 mV The two values are displayed in the RSSI levels register The command is intended for diagnostic purposes to set the correct RX_IN levels The optimum RX_IN input level is approximately 1 ...

Page 36: ...I with SS SPI without SS DATA_ DATA_CLK DATA_CLK DATA_CLK from master DATA_CLK from master CLK I O_7 A D 7 MOSI 1 data in reader in MOSI 1 data in reader in I O_6 A D 6 Direct mode data out sub carrier or bit stream MISO 2 data out MCU out MISO 2 data out MCU out I O_5 3 A D 5 Direct mode strobe bit clock out See Note 3 See Note 3 I O_4 A D 4 SS slave select 4 I O_3 A D 3 I O_2 A D 2 at VDD at VDD...

Page 37: ... volatile memory to the reader In non continuous address mode simple addressed mode only one data word is expected after the address Address mode is used to write or read the configuration registers or the FIFO When writing more than 12 bytes to the FIFO the continuous address mode should be set to 1 The command mode is used to enter a command resulting in reader action initialize transmission ena...

Page 38: ... the sequence of the data with an 8 bit address word first followed by data Communication is ended by the StopSmpl condition where the falling edge on the I O_7 pin is expected while CLK is high the StopCont condition where the I O_7 pin must have a successive rising and falling edge while CLK is low in order to reset the parallel interface and be ready for the new communication sequence The StopS...

Page 39: ...ion was completed incorrectly 5 6 2 Transmit Before beginning data transmission the FIFO should be cleared with a reset command 0F Data transmission is initiated with a selected command described in the Direct Commands section Table 5 29 The MCU then commands the reader to do a continuous write command 3Dh see Table 5 31 starting from register 1Dh Data written into register 1Dh is the TX length by...

Page 40: ...th read and continuous address mode bits set to 1 See Table 5 31 C Read 1 byte 8 bits from IRQ status register 0Ch D Dummy read 1 byte from register 0Dh collision position and interrupt mask E Stopping the dummy read a When using slave select SS set SS bit high b When not using SS stop condition when SCLK is high See Table 5 30 5 7 1 SPI Interface Without SS Slave Select Pin The serial interface w...

Page 41: ...RF7960 TRF7961 www ti com SLOU186F AUGUST 2006 REVISED AUGUST 2010 Figure 5 9 Serial SPI Interface Communication Write Mode Copyright 2006 2010 Texas Instruments Incorporated System Description 41 Submit Documentation Feedback focus ti com TRF7960 TRF7961 ...

Page 42: ...rising edge of SCLK after half a clock cycle valid data can be read on the MISO pin at the falling edge of SCLK It takes eight clock edges to read out the full byte MSB first Note When using the hardware SPI for example an MSP430 hardware SPI to implement the foregoing feature care must be taken to switch the SCLK polarity after write phase for proper read operation The example clock polarity for ...

Page 43: ...0 Figure 5 11 SPI Interface Communication Continuous Read Mode Note Special steps are needed to read the TRF796x IRQ status register register address 0x0C in SPI mode The status of the bits in this register is cleared after a dummy read The following steps must be followed when reading the IRQ status register 1 Write in command 0x6C read IRQ status register in continuous mode eight clocks 2 Read o...

Page 44: ... a single sequence is 12 bytes Note The number of bytes in a frame transmitted or received can be greater than 12 bytes During transmission the MCU loads the reader s FIFO or during reception the MCU removes data from the FIFO and the FIFO counter counts the number of bytes being loaded into the FIFO Meanwhile the byte counter keeps track of the number of bytes being transmitted An interrupt reque...

Page 45: ... requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe Th...

Page 46: ... P1 mm W mm Pin1 Quadrant TRF7960RHBR QFN RHB 32 3000 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 TRF7960RHBT QFN RHB 32 250 180 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 TRF7961RHBR QFN RHB 32 3000 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 TRF7961RHBT QFN RHB 32 250 180 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 PACKAGE MATERIALS INFORMATION www ti com 14 Jul 2012 Pack Materials Page 1 ...

Page 47: ...gth mm Width mm Height mm TRF7960RHBR QFN RHB 32 3000 367 0 367 0 35 0 TRF7960RHBT QFN RHB 32 250 210 0 185 0 35 0 TRF7961RHBR QFN RHB 32 3000 367 0 367 0 35 0 TRF7961RHBT QFN RHB 32 250 210 0 185 0 35 0 PACKAGE MATERIALS INFORMATION www ti com 14 Jul 2012 Pack Materials Page 2 ...

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Page 51: ...regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequence...

Page 52: ...ause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one of the following measures Reorient or relocate the...

Page 53: ... NOTE In the event that these conditions cannot be met for example certain laptop configurations or co location with another transmitter then the FCC authorization is no longer considered valid and the FCC ID cannot be used on the final product In these circumstances the OEM integrator will be responsible for re evaluating the end product including the transmitter and obtaining a separate FCC auth...