SLOU186F
–
AUGUST 2006
–
REVISED AUGUST 2010
5.7.2.1
FIFO Operation
The FIFO is a 12-byte register at address 1Fh with byte storage locations 0 to 11. FIFO data is loaded in a
cyclical manner and can be cleared by a reset command (0F).
Associated with the FIFO are two counters and three FIFO status flags. The first counter is a 4-bit FIFO
byte counter (bits B0
–
B3 in register 1Ch) that keeps track of the number of bytes loaded into the FIFO. If
the number of bytes in the FIFO is n, the register value is n
–
1 (number of bytes in FIFO register). If 8
bytes are in the FIFO, the FIFO counter (bits B0
–
B3 in register 1Ch) has the value 7.
A second counter (12 bits wide) indicates the number of bytes being transmitted (registers 1Dh and 1Eh)
in a data frame. An extension to the transmission-byte counter is a 4-bit broken-byte counter also provided
in register 1Eh (bits B0-B3). Together these counters make up the TX length value that determines when
the reader generates the EOF byte.
FIFO status flags are as follows:
1. FIFO overflow (bit B4 of register 1Ch)
–
indicates that the FIFO was loaded too soon
2. FIFO level too low (bit B5 of register 1Ch)
–
indicates that only three bytes are left to be transmitted
(Can be used during transmission)
3. FIFO level high (bit B6 of register 1Ch)
–
indicates that nine bytes are already loaded into the FIFO
(Can be used during reception to generate a FIFO reception IRQ. This is to notify the MCU to service
the reader in time to ensure a continuous data stream.)
During transmission, the FIFO is checked for an almost-empty condition, and during reception for an
almost-full condition. The maximum number of bytes that can be loaded into the FIFO in a single
sequence is 12 bytes. (Note: The number of bytes in a frame, transmitted or received, can be greater than
12 bytes.)
During transmission, the MCU loads the reader's FIFO (or during reception the MCU removes data from
the FIFO), and the FIFO counter counts the number of bytes being loaded into the FIFO. Meanwhile, the
byte counter keeps track of the number of bytes being transmitted. An interrupt request is generated if the
number of bytes in the FIFO is less than 3 or greater than 9, so that MCU can send new data or remove
the data as necessary. The MCU also checks the number of data bytes to be sent, so as to not surpass
the value defined in TX length bytes. The MCU also signals the transmit logic when the last byte of data is
sent or was removed from the FIFO during reception. Transmission starts automatically after the first byte
is written into FIFO.
5.8
External Power Amplifier Application
Applications requiring an extended read range can use an external power amplifier together with the
TRF7960/61. This can be implemented by adding an external power amplifier on the transmit side and
external sub-carrier detectors on the receive side.
To implement the external power amplification feature, certain registers must be programmed as shown
below.
1. Set bit B6 of the Regulator and I/O Control register to 1 (see
).
This setting has two functions, first to provide a modulated signal for the transmitter if needed, and
second to configure the TRF7960/61 receiver inputs for an external demodulated sub-carrier input.
2. Set bit B3 of the modulation and SYS_CLK control register to 1 (see
This function configures the ASK / OOK pin for either a digital or analog output (B3 = 0 enables a
digital output, B3 = 1 enables an analog output).
44
System Description
Copyright
©
2006
–
2010, Texas Instruments Incorporated
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