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SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
The framing section also supports the bit-collision detection as specified in ISO/IEC 14443 A and
ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ
Status register (0x0C). For ISO/IEC 14443 A specifically, the position of the bit collision is written in two
registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt
Mask register (0x0D) (bits B6 and B7).
The collision position is presented as sequential bit number, where the count starts immediately after the
start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these
registers when their contents are combined after being read. (the count starts with 0 and the first 16 bits
are the command code and the number of valid bits [NVB] byte).
The receive section also includes two timers. The RX wait time timer is controlled by the value in the RX
Wait Time register (0x08). This timer defines the time interval after the end of the transmit operation in
which the receive decoders are not active (held in reset state). This prevents false detections resulting
from transients following the transmit operation. The value of the RX Wait Time register (0x08) defines the
time in increments of 9.44 µs. This register is preset at every write to ISO Control register (0x01)
according to the minimum tag response time defined by each standard.
The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer
measures the time from the start of slot in the anticollision sequence until the start of tag response. If there
is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status
register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The
wait time is stored in the register in increments of 37.76 µs. This register is also automatically preset for
every new protocol selection.
6.7.1
Received Signal Strength Indicator (RSSI)
The TRF7963A incorporates three independent RSSI building blocks: Internal Main RSSI, Internal
Auxiliary RSSI, and External RSSI. The internal RSSI blocks are measuring the amplitude of the
subcarrier signal, and the external RSSI block measures the amplitude of the RF carrier signal at the
receiver input.
6.7.1.1
Internal RSSI – Main and Auxiliary Receivers
Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal
(subcarrier). Internal Main RSSI and Internal Auxiliary RSSI are identical except that they are connected to
different RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path
conditions.
The Internal RSSI values can be used to adjust the RX gain settings or decide which RX path (main or
auxiliary) provides the greater amplitude and, hence, to decide if the MUX may need to be reprogrammed
to swap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read
after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by
the reader. This guarantees an updated RSSI measurement for each new tag response.
The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range
is 600 mVpp to 4.2 Vpp with a typical step size of approximately 600 mV. Both RSSI values "Internal
Main" and "Internal Aux" RSSI are stored in the RSSI Levels and Oscillator Status register (0x0F).
shows the nominal relationship between the input RF peak level and the RSSI value.
