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5.1.2

Instrument Options

5.1.3

Data Capture Options

5.1.4

Test Options

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User Interface

The Instrument Options menu tab contains two options: Reinitialize Instrument and Read ADC EVM Setup
Procedure.

The Reinitialize Instrument option causes the TSW1200 software to reset itself to initial conditions and to
read the firmware settings from the TSW1200EVM again. The firmware and software revisions then are
displayed in the status window. This command is useful for cases where the jumper settings on the
TSW1200EVM may have changed since the TSW1200 software was opened, or in cases where the USB
connection to the PC has been dropped and the COM port must be reopened.

The Read ADC EVM Setup Procedure command causes the TSW1200 software to read a comment string
from the ini file for the ADC that is currently selected and then display that comment string in the status
pane. This comment string generally contains necessary setup information pertaining to the ADC EVM,
such as possibly requiring a non-default data format or required jumper setting for the EVM to
communicate properly with the TSW1200EVM.

The Data Capture menu tab contains two options: Capture Options and UART Baud Rate.

Capture Options allows for continuous capture that can be checked or unchecked. Continuous capture
causes the capture button to continuously capture, process, and display test data. Once the results are
displayed, the capture process automatically begins again at the desired capture interval The default
capture interval is zero, which means that the next capture is started once the current results are
displayed. The capture interval can be set in seconds to make the continuous capture less frequent.

The UART baud rate can be set to one of four data rates. This controls the data rate of unloading the
FIFO capture from the TSW1200EVM FPGA to the USB port. The UART baud rate is the limiting factor for
the time it takes to capture long record lengths of data. The UART data rate is commonly set to 460800,
as 921600 is not recommended for reliable data transfer.

The Test Options menu tab allows for setting the parameter options for the Single Tone FFT test and the
Time Domain test. Later revisions of the TSW1200 software will allow for setting test parameters for a
Dual Tone FFT test and the ACPR test.

For a Single Tone FFT test, the RMS line may be enabled or disabled. When enabled, a horizontal marker
is displayed over the FFT plot to indicate the RMS average of the noise floor of the FFT plot. The RMS
average is computed over all of the FFT bins except the bin containing the input frequency. More
precisely, the RMS line = SINAD + FFT Record Length Process Gain where FFT Record Process Gain =
10log(number of points/2).

SNR, SFDR, and SINAD can be expressed in either dBc or dBFS as selected by the dBFS selection
under the Single Tone FFT options.

By default, the noise calculations for SNR and SINAD do not include the five FFT bins around the
expected input frequency or the first five FFT bins at DC. The rest of the FFT bins out to the Nyquist
frequency are included in the calculation of the total noise. Vertical marker cursors are present in the FFT
display that indicate the beginning and the end of the bandwidth of interest for noise calculations. Because
these vertical markers are located at the extreme left-most and right-most positions on the FFT display,
these vertical markers often are not noticeable. It is possible to compute the total noise power over a
narrower range than the default DC through Nyquist band of frequencies. An integration band for the noise
calculations can be set in two ways. First, the mouse can be used to click on one of the vertical cursors
and drag it to a new desired location. Second, the Cursor Band Location window under the Single Tone
FFT Test Option in the tool bar can be used to set a new frequency band of integration for the calculation
of the total noise power.

Also excluded from calculation of the SNR is the power in the first five harmonics of the input frequency.
These first five harmonics are included in calculation of SINAD (signal to noise and distortion) and thus
this is the principal difference between SNR and SINAD. (SINAD is sometimes called SNDR, signal to
noise and distortion ratio.) The number of harmonics to exclude from SNR can be set to a value other than
the default 5 in the Number of Harmonics window in the Single Tone FFT Test Option in the toolbar.

SLAU212A – April 2007 – Revised August 2008

TSW1200EVM: High-Speed LVDS Deserializer and Analysis System

17

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Summary of Contents for TSW1200EVM

Page 1: ...1200 User Interface Installation 13 8 Hardware Device Manager 14 9 Found New Hardware Windows 15 10 User Interface Initial Setup Screen 16 11 User Interface Single FFT format 20 12 User Interface Time...

Page 2: ...EW is a trademark of National Instruments Corporation MATLAB is a trademark of The MathWorks Inc Xilinx is a trademark of Xilinx Inc TSW1200EVM High Speed LVDS Deserializer and Analysis System 2 SLAU2...

Page 3: ...DS line one bit at a time at a higher data rate than the sample rate of the ADC The firmware in the FPGA on the TSW1200 is designed to accommodate both parallel DDR formats and serial LVDS formats alt...

Page 4: ...e ended CMOS output The TSW1200 FPGA has enough FIFO buffer to capture as much as a 65536 sample record length from the continuous sample data stream coming from the LVDS ADC interface The TSW1200 FPG...

Page 5: ...N TI recommends that the black banana jack J14 be connected to a bench ground even if the 6 V external power brick is connected to J7 Intermittent loss of the USB connection can sometimes be observed...

Page 6: ...FPGA Bit file CFG1 jumper J10 set to LO and jumper J11 set to HI is defined for use with ADC EVMs that employ a parallel LVDS DDR dual data rate format Bit file CFG2 is defined for use with ADC EVMs t...

Page 7: ...one JTAG device connected to the TDI of the next JTAG device The normal setting of the JTAG jumpers is to connect the TDI of the JTAG connector to the TDI pin of the FPGA EEPROM through jumper J12 pi...

Page 8: ...derived from the onboard oscillator LED D2 labeled DCM on the TSW1200 silkscreen which is an abbreviation for the digital clock manager block of logic in the FPGA flashes when an LVDS clock from the...

Page 9: ...amtec connector Fourteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1200EVM and many TI ADC EVMs For the parallel LVDS DDR...

Page 10: ...he operational mode of the ADC under evaluation There SPI signals are by default not connected on the ADC EVM until a 0 resistor is installed on the EVM to enable control of the SPI port from the TSW1...

Page 11: ...ure depth for an FFT on a million continuous data samples or more For this the output header posts are available so that a logic analyzer can be used to capture ADC data in real time The pinout of the...

Page 12: ...1200 Installation CD and are installed during the installation process The USB is accessed as a virtual communication port VCP and shows up in the Hardware Device Manager as TSW1200 under COM ports an...

Page 13: ...200 User Interface Installation If the TSW1200 user interface software is being installed on a machine that has an older version TI recommends that you first remove the old TSW1200 installation using...

Page 14: ...onnected the TSW1200EVM to the PC the TSW1200 can be located in the Hardware Device Manager as shown in Figure 8 The TSW1200 appears as TSW1200 as a COM port Each time the USB cable is connected it is...

Page 15: ...iguration for the PC If the Found New Hardware Wizard does appear again when the USB cable is reconnected follow the same responses to the dialog boxes as when the TSW1200 was first installed Figure 9...

Page 16: ...chosen from the test pulldown menu Figure 10 User Interface Initial Setup Screen The toolbar contains options and settings that are independent of the device selected for test or the test to be perfor...

Page 17: ...st Later revisions of the TSW1200 software will allow for setting test parameters for a Dual Tone FFT test and the ACPR test For a Single Tone FFT test the RMS line may be enabled or disabled When ena...

Page 18: ...nce statistics Time Domain displays the raw captured data in the format of a logic analyzer display and output level over time In the Window Display drop down menu the user chooses a windowing functio...

Page 19: ...marker to any place in the power spectrum such as a noise spur that is not already marked as a harmonic By default this additional marker initially goes to the highest spur that is not identified as...

Page 20: ...d third fourth and fifth harmonics of the input frequency and the user selectable marker are displayed in either dBFS or dBc Test setup Input parameters relevant to the test are repeated particularly...

Page 21: ...n results window In the upper half of the window the arithmetic value of the sample is represented on the vertical scale In the lower half of the window the individual bits of the data are displayed a...

Page 22: ...e can open a com port to the USB channel and can perform the register reads and writes to the TSW1200 hardware One common request for another user interface is MATLAB as the user might then want to us...

Page 23: ...1 2 C17 1uF C17 1uF 1 2 R109 300 R109 300 C44 01uF C44 01uF 1 2 C43 1uF C43 1uF 1 2 R58 24 3K R58 24 3K C349 10uF 10 16V C349 10uF 10 16V 1 2 C53 10uF 16V 10 LOW ESR C53 10uF 16V 10 LOW ESR C49 1uF C4...

Page 24: ...SDA 10 GND8 8 P3 3 30 P3 1 31 P3 0 32 GND28 28 X2 26 RI CP 16 DCD 15 VCC25 25 U1 4 XC4VLX25 SF363 BGA U1 4 XC4VLX25 SF363 BGA IO_L20P_7 R19 IO_L20N_VREF_7 R20 IO_L21P_7 R15 IO_L21N_7 R16 IO_L23P_VRN_7...

Page 25: ...F C79 10uF J10 HEADER 3 J10 HEADER 3 1 2 3 J2 J2 2 4 6 8 10 12 14 1 3 5 7 9 11 13 C86 1uF C86 1uF 1 2 R3 0 ohm R3 0 ohm C83 3 3uF C83 3 3uF R52 4 7K R52 4 7K R2 0 ohm R2 0 ohm R33 1K R33 1K Q3 DTC114E...

Page 26: ...6 IO_L4P_5 B17 IO_L4N_VREF_5 C17 IO_L5P_5 D16 IO_L5N_5 E16 IO_L6P_5 A18 IO_L6N_5 B18 IO_L7P_5 D17 IO_L7N_5 D18 IO_L8P_CC_LC_5 B19 IO_L8N_CC_LC_5 C20 IO_L9P_CC_LC_5 F18 IO_L9N_CC_LC_5 E18 IO_L10P_5 C18...

Page 27: ...10 8 9 J18 HDR 16X2 MALE 100CTR TI_SILKTEXT J18 HDR 16X2 MALE 100CTR TI_SILKTEXT 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 J6 HEADER MALE 20x2 POS 100 VERT...

Page 28: ...onic 10 10V 2 C77 C78 22 pF 603 GRM1885C2A220JA01D Murata 5 100V 2 C81 C85 0 1 F 603 ECJ 1VB1H104K Panasonic 10 50V 2 C82 C84 2 2 F 603 ECJ 1VB1A225K Panasonic 10 10V 1 C83 3 3 F TANT_B TAJB335K016R A...

Page 29: ...o 1 1 10W 8 R27 R30 22 603 RC0603FR 0722RL Yageo 1 1 10W R60 R63 6 R33 R34 R37 R 1K 603 ERJ 3EKF1001V Panasonic 1 1 10W 38 R46 R47 2 R35 R36 100 603 ERJ 3EKF1000V Panasonic 1 1 10W 1 R45 100K 603 ERJ...

Page 30: ...I Provide pad 1 U14 PTH03000W SMD_PWRMOD_EUT5 PTH03000WAS TI TI Provide 1 U15 TPS73225 SOT23 DBV5 TPS73225DBVT TI TI Provide 1 Y1 12MHz w 18pF smd_xtal_AMB3B ABM3B 12 000MHZ 10 1 Abracon U T 4 Screw 4...

Page 31: ...m Circuit Board Layout and Layer Stackup Figure 19 TSW1200C Layout Layer Two SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 31 Submit Documentation...

Page 32: ...ard Layout and Layer Stackup www ti com Figure 20 TSW1200C Layout Power Plane 32 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentatio...

Page 33: ...Circuit Board Layout and Layer Stackup Figure 21 TSW1200C Layout Ground Plane SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 33 Submit Documentatio...

Page 34: ...Board Layout and Layer Stackup www ti com Figure 22 TSW1200C Layout Layer 5 34 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation...

Page 35: ...i com Circuit Board Layout and Layer Stackup Figure 23 TSW1200C Layer 6 SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 35 Submit Documentation Feed...

Page 36: ...Board Layout and Layer Stackup www ti com Figure 24 TSW1200C Bottom Layer 36 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation F...

Page 37: ...com Circuit Board Layout and Layer Stackup Figure 25 Circuit Board Stackup SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 37 Submit Documentation F...

Page 38: ...uct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer...

Page 39: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wo...

Page 40: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW1200EVM...

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