background image

PROG_B

TDI_0

M0

M2

M1

DO

NE

CE

TDO_0

TDO

TCK

TMS

TDI

HSW

AP_EN

CC

LK

BUSY

PROMRESET

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

+1.8V

+3.3V

+1.8V

+3.3V

+3.3V

+3.3V

+3.3V

+3.3V

D6

D7

D5

D2

D4

D3

D0

D1

D0

D1

D2

D3

D4

D5

D6

D7

CH7-CLKOUT

SH5

CH7-D0

SH5

CH6-D1

SH5

CH6-D2

SH5

CH6-D3

SH5

CH6-D4

SH5

CH6-D5

SH5

CH6-D0

SH5

CH5-D3

SH5

CH5-D4

SH5

CH5-D5

SH5

CH5-D6

SH5

CH5-D7

SH5

CH5-D9

SH5

CH5-D10

SH5

CH5-D1

1

SH5

CH5-D12

SH5

CH5-D13

SH5

CH5-D8

SH5

CH6-CLKOUT

SH5

CH6-D7

SH5

CH6-D9

SH5

CH6-D10

SH5

CH6-D1

1

SH5

CH6-D6

SH5

CH6-D8

SH5

CH6-D12

SH5

CH6-D13

SH5

CH5-CLKOUT

SH5

CH5-D0

SH5

CH5-D2

SH5

CH5-D1

SH5

CH7-D3

SH5

CH7-D1

SH5

CH7-D2

SH5

CH7-D4

SH5

CH7-D12

SH5

CH7-D13

SH5

CH7-D5

SH5

CH7-D6

SH5

CH7-D7

SH5

CH7-D8

SH5

CH7-D9

SH5

CH7-D1

1

SH5

CH7-D10

SH5

JTAG

1.DEFAULTSETUPFORJ1ANDJ12

SHORT1AND3;SHORT2AND4

2.PROMCONFIGURATION

M0=M1=1

SETUPFORMASTERSELECTMAPOPERATION

M2=0

NOTES:

D7

GREEN

D7

GREEN

R4

10K

R4

10K

R35

100

R35

100

R1

0ohm

R1

0ohm

U2

XCF32PFSG48

U2

XCF32PFSG48

D3

D5

NC1

A4

D7

A6

VCCO

B2

CE

B4

CL

KO

UT

C2

D4

C5

CE

O

D2

GND

A1

GND

A2

OE/RESET

A3

D6

A5

VCCINT

B1

CLK

B3

D5

B5

GND

B6

BUS

Y

C1

NC2

C3

NC3

C4

VC

CO

C6

CF

D1

NC4

D3

NC5

D4

VC

CO

D6

TMS

E2

VCCINT

E1

NC7

E4

NC6

E3

D2

E5

TDO

E6

GND

F1

NC8

F2

NC10

F4

NC9

F3

GND

F5

GND

F6

TD

I

G1

NC

11

G2

REV_SEL0

G3

REV_SEL1

G4

VC

CO

G5

VC

CIN

T

G6

GND

H1

VC

CJ

H2

TC

K

H3

EN_

EX

T_

SE

L

H4

D1

H5

D0

H6

C4

.1uF

C4

.1uF

1

2

R55

ZERO

R55

ZERO

R32

0ohm

R32

0ohm

C1

10uF

C1

10uF

C6

.1uF

C6

.1uF

1

2

RN1

4.7K

RN1

4.7K

1

8

2

7

3

6

4

5

C5

.01uF

C5

.01uF

1

2

R7

330

R7

330

C3

.01uF

C3

.01uF

1

2

R54

49.9

R54

49.9

R6

4.7K

R6

4.7K

J1J1

1

2

4

3

C2

.1uF

C2

.1uF

1

2

SW2

RESET

SW2

RESET

1

2

SW3

PROGRAM

SW3

PROGRAM

1

2

C80

.1uF

C80

.1uF

1

2

R31

0ohm

R31

0ohm

R53

49.9

R53

49.9

U10

L

V7745DEV

-200MHz

U10

L

V7745DEV

-200MHz

OE

1

NC

2

GND

3

OUT

4

OUT

5

VCC

6

J12J12

1

2

4

3

R36

100

R36

100

C87

.1uF

C87

.1uF

1

2

C79

10uF

C79

10uF

J10

HEADER3

J10

HEADER3

1

2

3

J2J2

2

4

6

8

10

12

14

1

3

5

7

9

1

1

13

C86

.1uF

C86

.1uF

1

2

R3

0ohm

R3

0ohm

+

C83

3.3uF

+

C83

3.3uF

R52

4.7K

R52

4.7K

R2

0ohm

R2

0ohm

R33

1K

R33

1K

Q3

DTC1

14EET1

Q3

DTC1

14EET1

J1

1

HEADER3

J1

1

HEADER3

1

2

3

R34

1K

R34

1K

U1-1

XC4VLX25-SF363-BGA

U1-1

XC4VLX25-SF363-BGA

HSW

APEN_0

E13

CCLK_0

E1

1

D_IN_0

E9

CS_B_0

E8

INIT_B_0

E12

TDN_0

E10

RDWR_B_0

F9

TDP_0

F10

DONE_0

F1

1

PROG_B_0

F12

TDI_0

R9

TDO_0

R10

M2_0

R1

1

M0_0

R12

TMS_0

T8

TCK_0

T9

PWRDWN_B_0

T10

DOUT_BUSY_0

T1

1

M1_0

T12

VBA

TT_0

T13

IO_L1P_D31_LC_1

F15

IO_L1N_D30_LC_1

E15

IO_L2P_D29_LC_1

E6

IO_L2N_D28_LC_1

F6

IO_L3P_D27_LC_1

D15

IO_L3N_D26_LC_1

E14

IO_L4P_D25_LC_1

E7

IO_L4N_D24_VREF_LC_1

D6

IO_L5P_D23_LC_1

D13

IO_L5N_D22_LC_1

C13

IO_L6P_D21_LC_1

C8

IO_L6N_D20_LC_1

D8

IO_L7P_D19_LC_1

D12

IO_L7N_D18_LC_1

C12

IO_L8P_D17_CC_LC_1

C9

IO_L8N_D16_CC_LC_1

D9

IO_L1P_GC_CC_LC_3

B12

IO_L1N_GC_CC_LC_3

A1

1

IO_L2P_GC_VRN_LC_3

A10

IO_L2N_GC_VRP_LC_3

B9

IO_L3P_GC_LC_3

C1

1

IO_L3N_GC_LC_3

B1

1

IO_L4P_GC_LC_3

B10

IO_L4N_GC_VREF_LC_3

C10

IO_L5P_GC_LC_3

B13

IO_L5N_GC_LC_3

A13

IO_L6P_GC_LC_3

A8

IO_L6N_GC_LC_3

B8

IO_L7P_GC_LC_3

B14

IO_L7N_GC_LC_

A14

IO_L8P_GC_LC_3

A7

IO_L8N_GC_LC_3

B7

IO_L1P_D15_CC_LC_2

V16

IO_L1N_D14_CC_LC_2

V15

IO_L2P_D13_LC_2

V6

IO_L2N_D12_LC_2

V5

IO_L3P_D1

1_LC_2

T14

IO_L3N_D10_LC_2

U13

IO_L4P_D9_LC_2

U8

IO_L4N_D8_VREF_LC_2

T7

IO_L5P_D7_LC_2

V13

IO_L5N_D6_LC_1

1

V12

IO_L6P_D5_LC_2

V9

IO_L6N_D4_LC_2

V8

IO_L7P_D3_LC_2

U12

IO_L7N_D2_LC_2

V1

1

IO_L8P_D1_LC_2

V10

IO_L8N_D0_LC_2

U9

IO_L1P_GC_LC_4

W13

IO_L1N_GC_LC_4

W12

IO_L2P_GC_LC_4

Y5

IO_L2N_GC_LC_4

W5

IO_L3P_GC_LC_4

Y12

IO_L3N_GC_LC_4

Y1

1

IO_L4P_GC_LC_4

Y6

IO_L4N_GC_VREF_LC_4

W6

IO_L5P_GC_LC_4

W1

1

IO_L5N_GC_LC_4

W10

IO_L6P_GC_LC_4

Y7

IO_L6N_GC_LC_4

W7

IO_L7P_GC_VRN_LC_4

Y10

IO_L7N_GC_VRP_LC_4

Y9

IO_L8P_GC_CC_LC_4

W9

IO_L8N_GC_CC_LC_4

W8

www.ti.com

Schematics and Bill of Materials

Figure 15. Schematic Diagram Page 3

SLAU212A – April 2007 – Revised August 2008

TSW1200EVM: High-Speed LVDS Deserializer and Analysis System

25

Submit Documentation Feedback

Summary of Contents for TSW1200EVM

Page 1: ...1200 User Interface Installation 13 8 Hardware Device Manager 14 9 Found New Hardware Windows 15 10 User Interface Initial Setup Screen 16 11 User Interface Single FFT format 20 12 User Interface Time...

Page 2: ...EW is a trademark of National Instruments Corporation MATLAB is a trademark of The MathWorks Inc Xilinx is a trademark of Xilinx Inc TSW1200EVM High Speed LVDS Deserializer and Analysis System 2 SLAU2...

Page 3: ...DS line one bit at a time at a higher data rate than the sample rate of the ADC The firmware in the FPGA on the TSW1200 is designed to accommodate both parallel DDR formats and serial LVDS formats alt...

Page 4: ...e ended CMOS output The TSW1200 FPGA has enough FIFO buffer to capture as much as a 65536 sample record length from the continuous sample data stream coming from the LVDS ADC interface The TSW1200 FPG...

Page 5: ...N TI recommends that the black banana jack J14 be connected to a bench ground even if the 6 V external power brick is connected to J7 Intermittent loss of the USB connection can sometimes be observed...

Page 6: ...FPGA Bit file CFG1 jumper J10 set to LO and jumper J11 set to HI is defined for use with ADC EVMs that employ a parallel LVDS DDR dual data rate format Bit file CFG2 is defined for use with ADC EVMs t...

Page 7: ...one JTAG device connected to the TDI of the next JTAG device The normal setting of the JTAG jumpers is to connect the TDI of the JTAG connector to the TDI pin of the FPGA EEPROM through jumper J12 pi...

Page 8: ...derived from the onboard oscillator LED D2 labeled DCM on the TSW1200 silkscreen which is an abbreviation for the digital clock manager block of logic in the FPGA flashes when an LVDS clock from the...

Page 9: ...amtec connector Fourteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connector pinout that is common between the TSW1200EVM and many TI ADC EVMs For the parallel LVDS DDR...

Page 10: ...he operational mode of the ADC under evaluation There SPI signals are by default not connected on the ADC EVM until a 0 resistor is installed on the EVM to enable control of the SPI port from the TSW1...

Page 11: ...ure depth for an FFT on a million continuous data samples or more For this the output header posts are available so that a logic analyzer can be used to capture ADC data in real time The pinout of the...

Page 12: ...1200 Installation CD and are installed during the installation process The USB is accessed as a virtual communication port VCP and shows up in the Hardware Device Manager as TSW1200 under COM ports an...

Page 13: ...200 User Interface Installation If the TSW1200 user interface software is being installed on a machine that has an older version TI recommends that you first remove the old TSW1200 installation using...

Page 14: ...onnected the TSW1200EVM to the PC the TSW1200 can be located in the Hardware Device Manager as shown in Figure 8 The TSW1200 appears as TSW1200 as a COM port Each time the USB cable is connected it is...

Page 15: ...iguration for the PC If the Found New Hardware Wizard does appear again when the USB cable is reconnected follow the same responses to the dialog boxes as when the TSW1200 was first installed Figure 9...

Page 16: ...chosen from the test pulldown menu Figure 10 User Interface Initial Setup Screen The toolbar contains options and settings that are independent of the device selected for test or the test to be perfor...

Page 17: ...st Later revisions of the TSW1200 software will allow for setting test parameters for a Dual Tone FFT test and the ACPR test For a Single Tone FFT test the RMS line may be enabled or disabled When ena...

Page 18: ...nce statistics Time Domain displays the raw captured data in the format of a logic analyzer display and output level over time In the Window Display drop down menu the user chooses a windowing functio...

Page 19: ...marker to any place in the power spectrum such as a noise spur that is not already marked as a harmonic By default this additional marker initially goes to the highest spur that is not identified as...

Page 20: ...d third fourth and fifth harmonics of the input frequency and the user selectable marker are displayed in either dBFS or dBc Test setup Input parameters relevant to the test are repeated particularly...

Page 21: ...n results window In the upper half of the window the arithmetic value of the sample is represented on the vertical scale In the lower half of the window the individual bits of the data are displayed a...

Page 22: ...e can open a com port to the USB channel and can perform the register reads and writes to the TSW1200 hardware One common request for another user interface is MATLAB as the user might then want to us...

Page 23: ...1 2 C17 1uF C17 1uF 1 2 R109 300 R109 300 C44 01uF C44 01uF 1 2 C43 1uF C43 1uF 1 2 R58 24 3K R58 24 3K C349 10uF 10 16V C349 10uF 10 16V 1 2 C53 10uF 16V 10 LOW ESR C53 10uF 16V 10 LOW ESR C49 1uF C4...

Page 24: ...SDA 10 GND8 8 P3 3 30 P3 1 31 P3 0 32 GND28 28 X2 26 RI CP 16 DCD 15 VCC25 25 U1 4 XC4VLX25 SF363 BGA U1 4 XC4VLX25 SF363 BGA IO_L20P_7 R19 IO_L20N_VREF_7 R20 IO_L21P_7 R15 IO_L21N_7 R16 IO_L23P_VRN_7...

Page 25: ...F C79 10uF J10 HEADER 3 J10 HEADER 3 1 2 3 J2 J2 2 4 6 8 10 12 14 1 3 5 7 9 11 13 C86 1uF C86 1uF 1 2 R3 0 ohm R3 0 ohm C83 3 3uF C83 3 3uF R52 4 7K R52 4 7K R2 0 ohm R2 0 ohm R33 1K R33 1K Q3 DTC114E...

Page 26: ...6 IO_L4P_5 B17 IO_L4N_VREF_5 C17 IO_L5P_5 D16 IO_L5N_5 E16 IO_L6P_5 A18 IO_L6N_5 B18 IO_L7P_5 D17 IO_L7N_5 D18 IO_L8P_CC_LC_5 B19 IO_L8N_CC_LC_5 C20 IO_L9P_CC_LC_5 F18 IO_L9N_CC_LC_5 E18 IO_L10P_5 C18...

Page 27: ...10 8 9 J18 HDR 16X2 MALE 100CTR TI_SILKTEXT J18 HDR 16X2 MALE 100CTR TI_SILKTEXT 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 J6 HEADER MALE 20x2 POS 100 VERT...

Page 28: ...onic 10 10V 2 C77 C78 22 pF 603 GRM1885C2A220JA01D Murata 5 100V 2 C81 C85 0 1 F 603 ECJ 1VB1H104K Panasonic 10 50V 2 C82 C84 2 2 F 603 ECJ 1VB1A225K Panasonic 10 10V 1 C83 3 3 F TANT_B TAJB335K016R A...

Page 29: ...o 1 1 10W 8 R27 R30 22 603 RC0603FR 0722RL Yageo 1 1 10W R60 R63 6 R33 R34 R37 R 1K 603 ERJ 3EKF1001V Panasonic 1 1 10W 38 R46 R47 2 R35 R36 100 603 ERJ 3EKF1000V Panasonic 1 1 10W 1 R45 100K 603 ERJ...

Page 30: ...I Provide pad 1 U14 PTH03000W SMD_PWRMOD_EUT5 PTH03000WAS TI TI Provide 1 U15 TPS73225 SOT23 DBV5 TPS73225DBVT TI TI Provide 1 Y1 12MHz w 18pF smd_xtal_AMB3B ABM3B 12 000MHZ 10 1 Abracon U T 4 Screw 4...

Page 31: ...m Circuit Board Layout and Layer Stackup Figure 19 TSW1200C Layout Layer Two SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 31 Submit Documentation...

Page 32: ...ard Layout and Layer Stackup www ti com Figure 20 TSW1200C Layout Power Plane 32 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentatio...

Page 33: ...Circuit Board Layout and Layer Stackup Figure 21 TSW1200C Layout Ground Plane SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 33 Submit Documentatio...

Page 34: ...Board Layout and Layer Stackup www ti com Figure 22 TSW1200C Layout Layer 5 34 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation...

Page 35: ...i com Circuit Board Layout and Layer Stackup Figure 23 TSW1200C Layer 6 SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 35 Submit Documentation Feed...

Page 36: ...Board Layout and Layer Stackup www ti com Figure 24 TSW1200C Bottom Layer 36 TSW1200EVM High Speed LVDS Deserializer and Analysis System SLAU212A April 2007 Revised August 2008 Submit Documentation F...

Page 37: ...com Circuit Board Layout and Layer Stackup Figure 25 Circuit Board Stackup SLAU212A April 2007 Revised August 2008 TSW1200EVM High Speed LVDS Deserializer and Analysis System 37 Submit Documentation F...

Page 38: ...uct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer...

Page 39: ...siness practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product wo...

Page 40: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Texas Instruments TSW1200EVM...

Reviews: