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Introduction
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Functionality
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Introduction
The Texas Instruments TSW1200 High-Speed LVDS Deserializer and Analysis System provides a
comprehensive set of hardware and user interface software to effectively evaluate the performance of a
wide range of Texas Instruments (TI) high-speed, analog- to-digital converters (ADC), particularly those
high-speed ADCs that employ an low-voltage differential signal (LVDS) format for the data converter’s
output data. With a high-quality, low-jitter clock and a high-quality input frequency provided to the
evaluation module, the TSW1200 system can be used to demonstrate data sheet performance
specifications.
The TSW1200 hardware has a high-speed connector that plugs into an evaluation module (EVM) for the
ADC. Firmware for an FPGA on the TSW1200EVM has an interface to various LVDS data formats and
FIFO memory sufficient to capture as much as 64K samples of data. A USB connection transfers the
captured data to a personal computer for post-processing. The user Interface software controls the
TSW1200 hardware and displays the FFT and important statistics related to the performance of the ADC.
Many TI high-speed ADCs have LVDS outputs for the digitized data. These ADCs are generally available
on an EVM that connects directly to the TSW1200EVM. The common connector between the ADC EVM
and the TSW1200EVM is a Samtec high-speed connector suitable for differential pairs of pins separated
by ground. A common pinout for the connector across a family of EVMs has been established. At present,
the interface between the ADC EVM and the TSW1200EVM has defined connections for 14 pairs of LVDS
plus two clock lines. The connector pinout has an additional 14 LVDS pairs for future product support. In
most cases, if a TI ADC supports LVDS outputs, then the TSW1200 system can be used to capture data
from the ADC. If the ADC supports a CMOS single-ended format, then the TSW1100 system is intended
to interface to it.
The data format for the LVDS data bus can be in one of many formats, all supported by the TSW1200.
For single-channel, high-speed ADCs, the data format is commonly parallel dual-data rate with one clock
line. Dual-data rate means that both the rising and falling edges of the clock strobe data into the
TSW1200. For multichannel ADCs, the data is commonly presented in a serialized format, where
individual bits of the output data are presented on an LVDS line one bit at a time, at a higher data rate
than the sample rate of the ADC.
The firmware in the FPGA on the TSW1200 is designed to accommodate both parallel DDR formats and
serial LVDS formats, although not at the same time. The EEPROM on the TSW1200EVM is large enough
to hold two distinct program files for the FPGA. One program bit file supports the parallel DDR format and
the other bit file supports serial LVDS formats. The TSW1200 can be set to support the desired data
format by simply setting two jumpers and pressing the PROGRAM button.
The parallel DDR FPGA program supports several types of data formats. One common format presents
odd-numbered data bits on the bus on one clock edge and even-numbered data bits on the bus on the
other clock edge. This format is commonly used for ADCs with sampling rates up to 250 MHz. For this
bit-wise DDR format, the parallel data bus uses half as many LVDS pairs as there are bits in the sample.
For example, a 16-bit ADC uses eight LVDS pairs for data plus an LVDS clock pair for bit-wise DDR. For
higher sample rates up to 500 MHz, a sample-wise DDR format is often used. For sample-wise DDR, the
data bus width has as many LVDS pairs as the bit resolution of the ADC. On one clock edge, a data
sample from the ADC is registered; on the next clock edge, the next data sample from the ADC is
registered.
The serial FPGA program also supports several data formats. For one-wire serial formats, the data is
serialized onto a single LVDS pair at a rate that is 12 times the sample rate for an ADC with a 12-bit
resolution. A one-wire serialization format also is used for 14-bit and 16-bit data at data rates 14 or 16
times the sample rate, respectively. For serial data formats, a DDR LVDS bit clock is used to strobe the
serial data bits and to deserialize the data. An additional clock pair provided at the sample rate of the ADC
identifies the sample-word boundaries in the serial data. For multichannel ADCs, a single-bit clock and a
single sample-rate clock (frame clock) is used for all of the LVDS data channels. The other common serial
data format is two-wire serialization. Two-wire serialization is similar to one-wire serialization except that a
data channel uses two LVDS pairs to carry the serialized data at a rate that is half of what it is for one-wire
serialization. Two-wire serialization commonly is used for sample rates up to 125 MHz, whereas one-wire
serialization generally is used for sample rates up to 65 MHz.
SLAU212A – April 2007 – Revised August 2008
TSW1200EVM: High-Speed LVDS Deserializer and Analysis System
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