Basic Test Procedure with TSW1400
20
SLAU374B – December 2011 – Revised May 2016
Copyright © 2011–2016, Texas Instruments Incorporated
TSW308x Evaluation Module
TSW3085 EVM Jumpers: (make sure the following jumpers are at their default setting)
Reference Designator
Setting
Function
JP2
1-2
DAC3482 TXENABLE
JP3
2-3
DAC3482 SLEEP
JP4
1-2
10-MHz TCXO Enable
JP5
2-3
TRF3705 Power Down
JP1
2-3
TRF3705 Gain Control
SJP2
2-3
CPLD EEPROM W/P
SJP3
1-2
USB Bus Power
SJP4
1-2
CPLD Clock Select
SJP5
2-3
Internal/External Reference Select for LMK04806B OSCIN
SJP1, SJP6, SJP7, SJP8
2-3
DAC3482 DATACLK delay. Default is zero trace delay.
3.4
TSW308x Example Setup Procedure
1. Turn on power to both boards, and press the reset button SW1 on the TSW308xEVM.
2. Start the TSW308x EVM GUI program. When the program starts, press the
RESET USB Port
button in
the GUI, and verify USB communication.
3. Select the appropriate EVM platform on the software menu.
Figure 14. EVM Platform Selection
4. Click on
LOAD REGS
, browse to the installation folder, and load example files. The example files are
located at
C:\Program Files\Texas Instruments\TSW308x\Configuration Files
. To configure the
LMK04806B in single PLL mode, select the file in the LMK04806 PLL Mode 10-MHz reference folder.
To configure the LMK04806B in clock distribution mode, select the file in the
LMK04806 Clock
Distribution Mode
folder.
For the TSW3084, the files contain settings for 4x interpolation with the DAC3484 running at 1228.8
MSPS. The data rate for each DAC is at 307.2 MSPS. The NCO is enabled at 30 MHz.
For the TSW30H84, the files contain settings for 2x interpolation with the DAC34H84 running at 1228.8
MSPS. The data rate for each DAC is at 614.4 MSPS. The NCO is enabled at 30 MHz.
For the TSW3085, the files contain settings for 2x interpolation with the DAC3482 running at 1228.8
MSPS. The data rate for each DAC is at 614.4 MSPS. The NCO is enabled at 30 MHz.
5. Click on
Send All
to write all of the values to the devices. If the LMK04806B is programmed properly in
single PLL mode, the
LMK LOCK
LED (D7) near the device illuminates. The updated register
configuration for the LMK04806B now appears as shown in
6. Note: J5 (CLK6) is configured as a divide-by-100 CMOS clock. This is used to verify EVM functionality.