THCV242_ Rev.2.00_E
Copyright
©
2019 THine Electronics, Inc. THine Electronics, Inc.
34/53
Security E
Table 21.
MIPI output setting 2/2
Address
bit
R/W
Initial
0x1606
[7]
-
1'b0
[6:0]
R/W
7'b100_0000
0x1609
[7:0]
R/W
8'd4
0x160a
[7:0]
R/W
8'h1d
0x160b
[7:0]
R/W
8'h07
0x160c
[7:0]
R/W
8'h02
0x160d
[7:0]
R/W
8'h0c
0x160e
[7:0]
R/W
8'h0b
0x160f
[7:0]
R/W
8'h05
0x1610
[7:0]
R/W
8'h04
0x1611
[7:0]
R/W
8'h10
0x1612
[7:0]
R/W
8'h07
0x1614
[7:0]
R/W
8'h04
0x1615
[7:0]
R/W
8'h1d
0x1616
[7:0]
R/W
8'h07
0x1617
[7:0]
R/W
8'h02
0x1618
[7:0]
R/W
8'h0c
0x1619
[7:0]
R/W
8'h0b
0x161a
[7:0]
R/W
8'h05
0x161b
[7:0]
R/W
8'h04
0x161c
[7:0]
R/W
8'h10
0x161d
[7:0]
R/W
8'h07
0x161f
[7:4]
-
2'b00
[3:0]
R/W
4'h0
R_REQ_SEL
MIPI Tx Lane PORT assignment
[3]Lane3, [2]Lane2, [1]Lane1, [0]Lane0
0:PORT0
1:PORT1
-
Reserved
R_TX_THS_TRAIL1
Data lane TRAIL period setting PORT1
R_TX_THS_ZERO1
Data lane ZERO period setting PORT1
R_TX_THS_PREPARE1
Data lane Prepare period setting PORT1
R_TX_TLPX1
Data lane TLPX period setting PORT1
R_TX_THS_EXIT1
Data lane EXIT period setting PORT1
R_TX_CLK_POST1
CLK lane POST period setting PORT1
R_TX_CLK_PRE1
CLK lane PRE period setting PORT1
R_TX_CLK_TRAIL1
CLK lane TRAIL period setting PORT1
R_TX_CLK_ZERO1
CLK lane ZERO period setting PORT1
R_TX_CLK_PREPARE1
CLK lane PrePare period setting PORT1
R_TX_THS_TRAIL0
Data lane TRAIL period setting PORT0
R_TX_THS_ZERO0
Data lane ZERO period setting PORT0
R_TX_THS_PREPARE0
Data lane Prepare period setting PORT0
R_TX_TLPX0
Data lane TLPX period setting PORT0
R_TX_THS_EXIT0
Data lane EXIT period setting PORT0
R_TX_CLK_POST0
CLK lane POST period setting PORT0
R_TX_CLK_PRE0
CLK lane PRE period setting PORT0
R_TX_CLK_TRAIL0
CLK lane TRAIL period setting PORT0
R_TX_CLK_ZERO0
CLK lane ZERO period setting PORT0
R_TX_CLK_PREPARE0
CLK lane PrePare period setting PORT0
R_MODE_SET
[6] ReservedH: Must be set 1
[5:4] ReservedL: Must be set 0
[3:2] HBLANK CLK OFF
[3] HBLANK CLK OFF PORT1
0:OFF (HS clock off and go into LP at HBlank)
1:ON (HS clock continuously on at HBlank)
[2] HBLANK CLK OFF PORT0
0:OFF (HS clock off and go into LP at HBlank)
1:ON (HS clock continuously on at HBlank)
[1:0] CLK_NOT_STOP
[1] CLK_NOT_STOP PORT1
0:OFF (HS clock off at VBlank)
1:ON (HS clock permanently on)
[0] CLK_NOT_STOP PORT0
0:OFF (HS clock off at VBlank)
1:ON (HS clock permanently on)
"7'b100_1100" is typical usage
Register Name
Description
-
Reserved
