ISCLK/ISSTB . . . . . . .input stream clock for MPEG encoder
ISSYNC . . . . . . . . . . . .input stream sync for MPEG encoder
ISVLD . . . . . . . . . . . . .Input stream
KDB_RST . . . . . . . . . .KDB reset
LOGGER_CS . . . . . . . .Logger Test Board chip select
LOGGER_IRQ . . . . . . .Logger Test Board interrupt
MCAS_ . . . . . . . . . . . .Claudia SDRAM column address select
MCKE . . . . . . . . . . . . .Claudia SDRAM clock enable
MCLK . . . . . . . . . . . . .Claudia SDRAM clock
MCS_ . . . . . . . . . . . . . .Claudia SDRAM chip select
MDQMH . . . . . . . . . . .Claudia SDRAM byte 1 enable
MDQM . . . . . . . . . . . . .Claudia SDRAM byte 0 enable
MEMWAIT . . . . . . . . . .Memmory wait
MODEM_IRQ . . . . . . .Modem Interrupt (perpare)
MODEM_RST . . . . . . .Modem Reset (perpare)
MRAS . . . . . . . . . . . . .Claudia SDRAM row address select
MWE . . . . . . . . . . . . . .Claudia SDRAM write enable
NICAM_RST . . . . . . . .Nicam Reset
ODD_IRQ . . . . . . . . . .ODD Interrupt
ODD_RST . . . . . . . . . .ODD Reset
OE . . . . . . . . . . . . . . . .Output enable
OS0..7 . . . . . . . . . . . . .Output stream Data signal
OSCLK/OSSTB . . . . . .Output stream clock signal
OSREQ . . . . . . . . . . . .Output stream request signal
OSSYNC . . . . . . . . . . .Output stream sync signal
OSVLD . . . . . . . . . . . . .Output stream valid signal
OVHSYNC . . . . . . . . . .Output stream H-sync signal
OVVSYNC . . . . . . . . . .Output stream V-sync signal
PDIAG . . . . . . . . . . . . .IDE Diaquostic pin
PGND . . . . . . . . . . . . .PLL ground
PPC_CLK . . . . . . . . . .Clock for EMI SDRAM
PS_RST . . . . . . . . . . . .Progressive Scan reset
PS_V . . . . . . . . . . . . . .V-sync for Progressive Scan
PSTOP . . . . . . . . . . . . .Part of reset for MPEG encoder
PVDD2 . . . . . . . . . . . . .2.5V power supply for PLL
PWR_OK . . . . . . . . . . .Power ok
R_OUT . . . . . . . . . . . . .R/2H-Pr ouput from DXX
R_PR2H_DXX . . . . . . .R/2H-Pr ouput from low-pass filter
RAS0 . . . . . . . . . . . . . .Row address select 0
RESET . . . . . . . . . . . . .Reset
RING . . . . . . . . . . . . . .(prepare for Modem)
RLSD . . . . . . . . . . . . . .(prepare for Modem)
RNOTW . . . . . . . . . . . .Read nor write
RTS . . . . . . . . . . . . . . .(prepare for Modem)
RX_ELM . . . . . . . . . . .Receive Elmer
RXD1 . . . . . . . . . . . . . .Receive data 1
RXD2 . . . . . . . . . . . . . .Receive data 2
SDRA0..11 . . . . . . . . . .EMI SDRAM address
SDRADQMH . . . . . . . .EMI SDRAM byte 1 enable
SDRADQML . . . . . . . .EMI SDRAM byte 0 enable
SDRAM_WE . . . . . . . .EMI SDRAM write enable
SDRAMBA0 . . . . . . . .EMI SDRAM bank select
SDRAMCS0 . . . . . . . .EMI SDRAM column address select
SDRAMRAS . . . . . . . .EMI SDRAM row address select
SDRD0..15 . . . . . . . . .EMI SDRAM data
SLIDE_IN . . . . . . . . . . .ODD tray close control signal
SLIDE_OC . . . . . . . . . .ODD tray over-current detection
SLIDE_OUT . . . . . . . . .ODD tray open control signal
SPDIF . . . . . . . . . . . . .Sound Pro Digital Interface
SPDIF_DXX . . . . . . . . .SPDIF output from DXX
SYS_CS . . . . . . . . . . . .Bank0 (EMI SDRAM) chip select
SYS_RST . . . . . . . . . . .System reset
SYSCLK . . . . . . . . . . .System clock
TCK . . . . . . . . . . . . . . .Test clock of DXX JTAG
TDI . . . . . . . . . . . . . . . .Test data in of DXX JTAG
TDO . . . . . . . . . . . . . . .Test data out of DXX JTAG
TMS . . . . . . . . . . . . . . .Test mode select of DXX JTAG
TRESET . . . . . . . . . . . .Test reset of DXX JTAG
TRIG_IN . . . . . . . . . . . .Trigger in
TRIG_OUT . . . . . . . . . .Trigger out
TX_ELM . . . . . . . . . . . .Trasmit Elmer
TXD1 . . . . . . . . . . . . . .Transmit data 1
TXD2 . . . . . . . . . . . . . .Transmit data 2
USB+FRONT . . . . . . . .USB input +
USB-FRONT . . . . . . . .USB input -
V_1H . . . . . . . . . . . . . .V-sync for interlace mode
V_VBI . . . . . . . . . . . . . .V-sync for PIP (picture in picture)
- . . . . . . . . . . . . . . . . . .function
VBI_BL . . . . . . . . . . . .PIP blanking
VCCRAM . . . . . . . . . . .VCC for EMI SDRAM and SMI SDRAM
VCLKI . . . . . . . . . . . . .Video clock input
VCLKO . . . . . . . . . . . .Video clock output
VDDA . . . . . . . . . . . . . .Analog supply voltage for analog inputs
VDDE . . . . . . . . . . . . . .Digital supply voltage (peripheral cells)
VDDI . . . . . . . . . . . . . .Digital supply voltage 2 (core)
VDDX . . . . . . . . . . . . . .Supply voltage for crystal oscillator
VDEC_HS . . . . . . . . . .Video decoder H-sync output
VDEC_RST_N . . . . . . .Video decoder reset
VDEC_RTS0 . . . . . . . .Video decoder real time status output
VDEC_RTS1 . . . . . . . .Video decoder real time status output
VDEC_VCLK . . . . . . . .Video decoder clock output
VDEC_VID0..7 . . . . . . .Video decoder video data output
VDRAM . . . . . . . . . . . .Power 3.3V for SMI SDRAM and
- . . . . . . . . . . . . . . . . . .EMI SDRAM
VEI_SSTB . . . . . . . . . .VEIS Strobe
VEISRDY . . . . . . . . . . .VEIS Ready
VEISREQ . . . . . . . . . . .VEIS Request
VEISSYNC . . . . . . . . . .VEIS Ready
VFL . . . . . . . . . . . . . . .Power 3.3V for Flash
VID_ACTIVE . . . . . . . .Video active
VID_CLK . . . . . . . . . . .Video clock
VID_DET . . . . . . . . . . .Video detect
WE0 . . . . . . . . . . . . . . .Write enable 0
WE1 . . . . . . . . . . . . . . .Write enable 1
Y_DXX . . . . . . . . . . . . .Y output from low-pass filter
Y_OUT . . . . . . . . . . . . .Y output from DXX
DTH8005
First issue 12 / 04
