6 F 2 T 0 1 7 2
CBF TRIP
Binary output circuit
≥
1
REMOTE RESET
0.00 – 10.00s
0
t
[RESET]
S
R
F/F
≥
1
Tripping output relay
Reset button
+
BO#m
&
&
"Dl"
+
"Lat"
"Ins"
&
TBO
&
"Dw"
≥
1
Figure 2.10.2 Tripping Output for Adjacent Circuit Breakers
2.11 Application of Protection Inhibits
All GRE110 protection elements can be blocked by a binary input signal. This feature is useful in
a number of applications.
2.11.1 Blocked Overcurrent Protection
Conventional time-graded definite time overcurrent protection can lead to excessive fault clearance
times being experienced for faults closest to the source. The implementation of a blocked
overcurrent scheme can eliminate the need for grading margins and thereby greatly reduce fault
clearance times. Such schemes are suited to radial feeder circuits, particularly where substations
are close together and pilot cables can be economically run between switchboards.
Figure 2.11.1 shows the operation of the scheme.
Instantaneous phase fault and earth fault pick-up signals OC1 HS, and EF1 HS of OC1 and EF1
elements are allocated to any of the binary output relays and used as a blocking signal. OC2 and
EF2 protections are set with a short delay time. (For pick-up signals, refer to Figure 2.1.5 and
2.1.6.)
For a fault at F as shown, each relay sends the blocking signal to its upstream neighbor. The signal
is input as a binary input signal OC2 BLOCK and EF2 BLOCK at the receiving end, and blocks the
OC2 and EF2 protection. Minimum protection delays of 50ms are recommended for the OC2 and
EF2 protection, to ensure that the blocking signal has time to arrive before protection operation.
Inverse time graded operation with elements OC1 and EF1 are available with the scheme switch
[MOC1] setting, thus providing back-up protection in the event of a failure of the blocked scheme.
51
Summary of Contents for GRE110
Page 183: ...6 F 2 T 0 1 7 2 Appendix B Signal List 184 ...
Page 191: ...6 F 2 T 0 1 7 2 Appendix C Event Record Items 192 ...
Page 196: ...6 F 2 T 0 1 7 2 Appendix D Binary Output Default Setting List 197 ...
Page 199: ...6 F 2 T 0 1 7 2 Appendix E Relay Menu Tree 200 ...
Page 210: ...6 F 2 T 0 1 7 2 Appendix F Case Outline 211 ...
Page 211: ...6 F 2 T 0 1 7 2 Case Outline for model 400 401 420 421 820 and 821 212 ...
Page 212: ...6 F 2 T 0 1 7 2 Case Outline for model 402 and 422 213 ...
Page 213: ...6 F 2 T 0 1 7 2 Appendix G Typical External Connection 214 ...
Page 245: ...6 F 2 T 0 1 7 2 Appendix J Return Repair Form 246 ...
Page 249: ...6 F 2 T 0 1 7 2 Customer Name Company Name Address Telephone No Facsimile No Signature 250 ...
Page 250: ...6 F 2 T 0 1 7 2 Appendix K Technical Data 251 ...
Page 256: ...6 F 2 T 0 1 7 2 Appendix L Symbols Used in Scheme Logic 257 ...
Page 259: ...6 F 2 T 0 1 7 2 Appendix M Modbus Interoperability 260 ...
Page 289: ...6 F 2 T 0 1 7 2 Appendix N IEC60870 5 103 Interoperability 290 ...
Page 296: ...6 F 2 T 0 1 7 2 Appendix O PLC Default setting 297 ...
Page 298: ...6 F 2 T 0 1 7 2 Appendix P Inverse Time Characteristics 299 ...
Page 304: ...6 F 2 T 0 1 7 2 Appendix Q IEC61850 Interoperability 305 ...