260
6
F
2
S
0
8
5
0
•
Press 5 (=Logic circuit) on the Test screen to display the Logic circuit screen.
•
Enter 59 as a signal number to be observed at monitoring jack A and press the ENTER key.
Residual current level detection is verified as follows:
•
Apply three-phase rated voltage and single-phase test current IT (= 3Io).
Set IT to lag Va by DEFF characteristic angle DEF
θ
. (The default setting of DEF
θ
is 85°.)
•
Lower
Va to 10 V to generate a residual voltage. Changing the magnitude of IT while
retaining the phase angle with the voltages, and measure the current at which the element
operates. Check that the measured current magnitude is within
±
5% of the current setting.
Residual voltage level detection is verified as follows:
•
Set IT to rated current and the three-phase voltage to rated voltage. Lower the magnitude of
Va while retaining the phase angle with the current and measure the voltage Va at which the
element operates. Operating residual voltage is expressed by (VR-Va), where VR is the rated
voltage. Check that the (VR-Va) is within 5% of the residual voltage setting.
6.5.1.6 Inverse Definite Minimum Time Overcurrent Element (IDMT) OCI, EFI
The testing circuit is shown in Figure 6.5.1.8.
Single-phase
current
source
A
TB1
-2
-1
-7
-8
Ia
3Io
GRL100
Monitoring
jack
A
0V
Time
counter
TB4 -A16
-A17
E
DC
power
supply
+
−
Start
Stop
OV
Figure 6.5.1.8 Testing IDMT
One of the four inverse time characteristics can be set, and the output signal numbers of the
IDMT are as follows:
IT
θ
3Vo
Vb
Vc
Va
Va
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Summary of Contents for GRL100-701B
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