117
6
F
2
S
0
7
8
9
Press 4 (= Logic circuit) on the "Test" sub-menu screen to display the "Logic circuit"
screen.
Enter a signal number 44 to observe the DIF-A output at monitoring jack A and press the
ENTER
key.
Apply an infeed current to terminal TB1-1 and -2.
When the infeed current applied is larger than the setting of ik (pu) and smaller than
kp(2+p
1
)/2 + ik(2-p
1
)/4 (pu), characteristic DF1 is checked.
When the infeed current applied is larger than kp(2+ p
1
)/2 + ik(2- p
1
)/4 (pu), characteristic
DF2 is checked.
Note: When the default settings are applied, the critical infeed current which
determines DF1 checking or DF2 checking is 1.56
×
(CT secondary
rated current).
Apply an outflow current of the same magnitude and counterphase with the infeed current
to terminal TB1-9 and 10.
Decrease the out flow current in magnitude and measure the values at which the element
operates.
Check that the measured values are within 7% of the theoretical values.
For characteristic DF1, the theoretical outflow current is given by the following equation:
I
out
= (2
p
1
)(I
in
ik)/(2+p
1
) (pu)
where, p
1
= slope setting of DF1
ik = minimum operating current setting
When the default settings are applied, I
out
= [(I
in
0.3) / 3]× (CT secondary rated current).
For characteristic DF2, the theoretical outflow current is given by the following equation.
I
out
= [(2
p
2
)I
in
(2
p
1
)ik + 2(p
2
p
1
)kp]/(2+ p
2
) (pu)
where, p
2
= slope setting of DF2
kp = break point of DF1 and DF2
When the default settings are applied, I
out
= 0.43× (CT secondary rated current).
Operating time
The testing circuit is shown in Figure 6.5.4.
Summary of Contents for GRT100 Series
Page 142: ... 141 6 F 2 S 0 7 8 9 Appendix A Block Diagram ...
Page 144: ... 143 6 F 2 S 0 7 8 9 Appendix B Signal List ...
Page 159: ... 158 6 F 2 S 0 7 8 9 ...
Page 160: ... 159 6 F 2 S 0 7 8 9 Appendix C Variable Timer List ...
Page 162: ... 161 6 F 2 S 0 7 8 9 Appendix D Binary Output Default Setting List ...
Page 165: ... 164 6 F 2 S 0 7 8 9 ...
Page 166: ... 165 6 F 2 S 0 7 8 9 Appendix E Details of Relay Menu and LCD and Button Operation ...
Page 174: ... 173 6 F 2 S 0 7 8 9 Appendix F Case Outline Flush Mount Type Rack Mount Type ...
Page 179: ... 178 6 F 2 S 0 7 8 9 ...
Page 180: ... 179 6 F 2 S 0 7 8 9 Appendix G External Connections ...
Page 185: ... 184 6 F 2 S 0 7 8 9 ...
Page 200: ... 199 6 F 2 S 0 7 8 9 ...
Page 201: ... 200 6 F 2 S 0 7 8 9 Appendix J Return Repair Form ...
Page 205: ... 204 6 F 2 S 0 7 8 9 Customer Name Company Name Address Telephone No Facsimile No Signature ...
Page 206: ... 205 6 F 2 S 0 7 8 9 ...
Page 207: ... 206 6 F 2 S 0 7 8 9 Appendix K Technical Data ...
Page 220: ... 219 6 F 2 S 0 7 8 9 ...
Page 221: ... 220 6 F 2 S 0 7 8 9 Appendix M Symbols Used in Scheme Logic ...
Page 224: ... 223 6 F 2 S 0 7 8 9 ...
Page 225: ... 224 6 F 2 S 0 7 8 9 Appendix N Implementation of Thermal Model to IEC60255 8 ...
Page 228: ... 227 6 F 2 S 0 7 8 9 ...
Page 229: ... 228 6 F 2 S 0 7 8 9 Appendix O IEC60870 5 103 Interoperability and Troubleshooting ...
Page 241: ... 240 6 F 2 S 0 7 8 9 Appendix P Modbus Interoperability ...
Page 255: ... 254 6 F 2 S 0 7 8 9 ...
Page 256: ... 255 6 F 2 S 0 7 8 9 Appendix Q Inverse Time Characteristics ...
Page 259: ... 258 6 F 2 S 0 7 8 9 ...
Page 260: ... 259 6 F 2 S 0 7 8 9 Appendix R Failed Module Tracing and Replacement ...
Page 266: ... 265 6 F 2 S 0 7 8 9 Appendix S Ordering ...
Page 269: ... 268 6 F 2 S 0 7 8 9 3 1 Oct 2 2017 Republished under spin off company ...
Page 270: ......