Preliminary User's Manual l MBLS1012AL UM 0001 l © 2019, TQ-Systems GmbH
Page 10
4.2.4
Gigabit Ethernet (Link)
TQMLS1012AL
DP83867
SGMII
RJ45
(X23)
ETH_LNK_RST#
ETH_LINK_PWRDWN#
EMI1
Illustration 7:
Block diagram Ethernet Link
When using the MBLS1012AL e.g. as router or switch, the single port can be used as LINK interface e.g. to a modem.
The single Ethernet port is provided via the PHY DP83867 at the SGMII interface (SerDes-Lane A).
The PHY has boot straps to start with configurable default values. Some boot straps can be customized with assembly options.
Further information is available in the latest circuit diagram of the MBLS1012AL.
The following table shows the pin assignment of the Ethernet connector.
Table 8:
Pinout RJ-45 connector X23 for “Link“
Pin
Name
Target pin / Net
Remark
1
GND
GND
–
2
TD1+
TD_P_A
–
3
TD1–
TD_M_A
–
4
TD2+
TD_P_B
–
5
TD2–
TD_M_B
–
6
TD3+
TD_P_C
–
7
TD3–
TD_M_C
–
8
TD4+
TD_P_D
–
9
TD4–
TD_M_D
–
10
GND
GND
–
11
GREEN_ANODE
V_2V5
82 Ω in series
12
GREEN_KATODE
LED_0 (DP83867)
Switched with transistor
13
YELLOW_ANODE
V_2V5
82 Ω in series
14
YELLOW_KATODE
LED_2 (DP83867)
Switched with transistor
The possible data throughput is influenced by the system load and the software platform used.
With the MBLS1012AL and the standard BSP, the following transfer rates can be achieved.
Table 9:
Characteristics Gigabit Ethernet X23 (Link)
Parameter
Min.
Typ.
Max.
Unit
Upstream
–
–
940
Mbit/s
Downstream
–
–
840
Mbit/s
Illustration 8:
Position of Gigabit Ethernet X23 (Link)
