User's Manual l MBLS1028A UM 0100 l © 2020, TQ-Systems GmbH
Page 27
4.5
Diagnostic interfaces
4.5.1
JTAG
®
The JTAG
®
port of the LS1028A on the TQMLS1028A is routed to a standard ARM
®
20-pin JTAG
®
connector.
The JTAG
®
signals of the TQMLS1028A are routed to an OpenSDA microcontroller via level shifters.
Between level shifter and MBLS1028A are tri-state buffers, which are switched by the firmware of the OpenSDA.
The JTAG
®
port of the microcontroller for the OpenSDA interface is routed to a 10-pin JTAG
®
connector with standard ARM
pinout. For the OpenSDA circuitry see chapter 4.5.2.
A Lauterbach debugger is intended for programming the TQMLS1028A. The JTAG
®
interface has no ESD protection.
Figure 20: Block diagram JTAG
®
The following table shows the pin assignment of the JTAG
®
connector.
Table 24:
Pinout JTAG
®
header, X34
Pin
Signal
Remark
1
JTAG_VREF
100 Ω in series to 1.8 V, use only as reference
2
1.8 V
0 Ω in series to 1.8 V
3
JTAG_TRST#
10 kΩ PU to 1.8 V
4
DGND
–
5
JTAG_TDI
10 kΩ PU to 1.8 V
6
DGND
–
7
JTAG_TMS
10 kΩ PU to 1.8 V
8
GND_DETECT
10 kΩ PU to 1.8 V – OpenSDA interface
9
JTAG_TCK
–
10
DGND
–
11
NC
10 kΩ to DGND
12
DGND
–
13
JTAG_TDO
–
14
DGND
–
15
JTAG_SRST#
10 kΩ PU to 1.8 V, Open-Drain-Buffer at JTAG_SRST#_3V3
16
DGND
–
17
1.8 V
10 kΩ to 1.8 V
18
DGND
–
19
DGND
10 kΩ to DGND
20
DGND
–