Advanced Setup
BXT7059 / BXTS7059 Technical Reference
PCI Sub-System Settings (continued)
Option Description
PERR# Generation
Disabled
/Enabled
PCI Express Settings
There are several sections associated with this BIOS parameter setting as shown
below. Short operational descriptions for each setting can be found in the upper
left corner of the BIOS set-up screen.
PCI Express Device Register Settings
Relaxed Ordering:
Disabled/Enabled
(bold
= default setting)
Extended Tag:
Disabled/Enabled
No Snoop:
Disabled/Enabled
Maximum Payload:
Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes,
2048Bytes, 4096 Bytes
Maximum Read Request:
Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes,
2048Bytes, 4096 Bytes
PCI Express Link Register Settings
ASPM Support:
Auto/Disabled
Extended Sync:
Disabled/Enabled
Link Training Retry:
Disabled, 2, 3, 5
Link Training Timeout:
10 – 1000 usec with 100 usec being the default value
Unpopulated Links:
Keep Link On, Disabled
PCI Express GEN2
Settings
There are several PCIe 2.0/3.0 sections associated with this BIOS parameter
setting as shown below. Short operational descriptions for each setting can be
found in the upper left corner of the BIOS set-up screen.
PCI Express Device Register Settings
Completion Timeout:
Default/Shorter/Longer/Disabled
The default setting
enables the normal link timeout range of 50us to 50ms. These BIOS selections
allow you to vary this setting as need in you system design.
ARI Forwarding:
Disabled/Enabled
AtomicOp Requester Enable:
Disabled/Enabled
AtomicOp Egress Block:
Disabled/Enabled
IDO Request Enable:
Disabled/Enabled
IDO Completion Enable:
Disabled/Enabled
LTR Mechanism Enable:
Disabled/Enabled
End-END TLP Prefix B1:
Disabled/Enabled
PCI Express GEN2 Link Register Settings
Target Link Speed:
Auto, Force to 2.5 GT/s, Force to 5.0 GT/s
Clock Power Management:
Disabled/Enabled
Compliance SOS:
Disabled/Enabled
Hardware Autonomous Width:
Disabled/Enabled
Hardware Autonomous Speed:
Disabled/Enabled
Trenton
Systems
Inc.
2-2
