TE0600 TRM
Revision: V3.02
Copyright © 2017 Trenz Electronic GmbH
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Xilinx Spartan-6 LX FPGA
clock generator
10/100/1000 Mbps Ethernet PHY
protected 1-Wire EEPROM
DDR3-SDRAM
DC-DC converters
Bottom side:
B2B connector J1
B2B connector J2
Flash memory
Key features
Industrial-grade Xilinx Spartan-6 LX FPGA micromodule (LX45 / LX100 / LX150)
10/100/1000 tri-speed Gigabit Ethernet transceiver (PHY)
2 x 16-bit-wide 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM
128 Mb (16 MB) SPI Flash memory (for configuration and operation) accessible through:
1 kb protected 1-Wire EEPROM with SHA-1 Engine
JTAG port (SPI indirect)
FPGA configuration through:
B2B connector
JTAG port
SPI Flash memory
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/O pins available on B2B
strips
4.0 A x 1.2 V power rail
1.5 A x 1.5 V power rail
125 MHz reference clock signal
Single-ended custom oscillator (option)
eFUSE bit-stream encryption (LX100 or larger)
1 user LED
Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
Storage device name
Content
Notes
SPI Flash memory
Blinky Demo
protected 1-Wire EEPROM
not programmed
