1
1
2
2
3
3
4
4
D
D
C
C
B
B
A
A
Date:
Page
3
of
7
Number:
Title:
CYC1000 - FPGA
02
Rev.
A4
Copyright:
Trenz Electronic GmbH
FPGA.SchDoc
Filename:
2017-11-21
default
TEI0003
3.3V
6.3V
X5R
C48
100nF
GND
3.3V
6.3V
X5R
C34
100nF
GND
i
B2
i
B3
GND
GND
GND
USER_BTN
3.3V
BDBUS1
BDBUS2
BDBUS3
BDBUS0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
BDBUS4
BDBUS5
GND
CLK12M
D6
D7
D8
D9
D10
D11
D12
D13
D14
3.3V
6.3V
X5R
C30
100nF
GND
D12_R
D11_R
i
B5
DEVCLRN
DEV_OE
1%
R49
12K
3.3V
3.3V
GND
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
CKE
RAS
CAS
WE
CS
3.3V
6.3V
X5R
C51
100nF
GND
i
B4
GND
GND
D2
D3
D4
D5
D0
D1
3.3V
6.3V
X5R
C50
100nF
GND
GND
i
B8
GND
GND
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN
AIN7
AREF
1%
R18
1R
6.3V
X5R
C15
100nF
GND
U1B
10CL025YU256C8G
U1C
10CL025YU256C8G
U1D
10CL025YU256C8G
U1E
10CL025YU256C8G
U1H
10CL025YU256C8G
VCCINT
GND
GND
GND
GND
VCCINT
VCCINT
VCCINT
VCCINT
BANK2_12
BANK2_13
BANK5_4
BANK5_5
BANK5_7
BANK5_8
BANK5_10
i
B5
BANK3_4
BANK3_18
BANK3_19
BANK3_20
BANK3_21
i
B3
BANK4_2
BANK4_3
BANK4_4
BANK4_6
BANK4_13
BANK4_14
BANK4_15
i
B8
i
B8
i
B2
VCCINT
GND
GND
GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM0
DQM1
3.3V
6.3V
X5R
GND
i
B7
GND
GND
GND
BANK7_19
U1G
10CL025YU256C8G
CLK
ADBUS7
ADBUS4
GND