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S1564-001-01 www.tyan.com
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Speculative Leadoff
The 430HX chipset is capable of allowing a DRAM read request to be
generated slightly before the address has been fully decoded. This can
reduce all read latencies.
More simply, the CPU will issue a read request and included with this
request is the place(address) in memory where the desired data is to be
found. This request is received by the DRAM controller. When enabled,
the controller will issue the read command slightly before it has finished
determining the address.
The default is disabled.
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Turn-Around Insertion
When this is enabled, the chipset will insert one extra clock to the
turn-around of back to back DRAM cycles.
The default is disabled.
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System BIOS Cacheable
When enabled, accesses to the system BIOS ROM addressed at
F0000H-FFFFFH are cached. Enable this for best performance under
DOS/Windows or Windows95. When using operating systems that do
not access the BIOS (Unix, OS/2, NT, etc...) this setting can be
disabled.
The default is enabled.
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Video BIOS Cacheable
As with caching the system BIOS above, enabling the Video BIOS
cache will cause access to the video BOS addressed at C0000h to
C7FFFFh to be cached.
The default is enabled.
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8/16 bit I/O Recovery Time
The recovery time is the length of time measured in CPU clocks, which
the system will delay after the completion of an I/O request. This delay
takes place because the CPU is operationg so much faster than the
I/O bus that the CPU must be delayed to allow for the completion of the
I/O request. This option allows you to determine the recovery time
allowed for 8/16 bit I/O.
The default is 1 clock cycle.
