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S1564-001-01 www.tyan.com
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Refresh Rate
Allows the refresh rate to be set according to the memory bus clock
(50mhz, 60mhz or 66mhz).
The default depends on CPU speed.
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Turbo Read LeadOff
A feature to enable the skipping of the first input register in the DRAM
data pipeline. This results in a 1 HCLK savings of all READ leadoff
timings.
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Read/Write Burst Timing
Allows customizing of the read timings in the memory design.
The options are x2222, x3333 and x4444. The lower the number, the
faster the DRAM will be accessed.
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Fast RAS to CAS Delay (Clocks)
If enabled, the row miss leadoff timing delay is set to 2 clocks, other
wise it is set to 3 clocks.
The default is 7/6/3/4.
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LeadOff Timing
This bit controls additional DRAM timings. This includes: Read
LeadOff, Write LeadOff, RAS# Precharge, and Refresh RAS asser-
tion.
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Turbo Read Pipelining
This bit affects the Read timings.
The options are enabled or disabled. The default is disabled.
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Speculative LeadOff
In this mode the DRAM controller read request is presented before the
final memory target (main memory, cache, or PCI) is decoded. This
results in a 1 HCLK increase in DRAM read leadoff latencies.
The default is disabled.
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Turn-Around Insertion
When enabled the chipset inserts 1 extra clock of turnaround on the MD
lines after asserting memory write enable (MWE#).
