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♦
Memory Address Drive Strength
This setup option allows the selection of memory address output buffer
drive affecting the MA(memory address) and MWE#(memory write
enale)pins.
The default is 8ma/8ma.
♦
NA Disable (NAD) For External Cache
When enabled the NA#(next address) pin is never asserted, otherwise
the assertion is dependent upon the cache type and size.
The default is enabled.
♦
Peer Concurrency
When enabled the CPU will be allowed to run DRAM/L2 cycles when
non-PHLD( PCI masters are running non-locked cycles targeting PCI
peer devices.
The default is enabled.
♦
ECC Test
This is a test mode described in the 430HX( Xcellerated Controller)
external design specification. This should be enabled only when using
ECC memory.
The default is disabled.
♦
DRAM Data Integrity Mode
This option allows the selection of the DRAM error detection. Either
parity or ECC modes are supported.
The default is parity.
♦
SERR# (System Error)Output Type
This allows the selection of the output type of the SERR# signal. Valid
options are Open drain and Normal (actively driven high).
The default
is normal.
♦
SERR#(System Error) Duration Mode
This option allows the determination of the SERR# output’s duration
when it is asserted. The modes are Pulse (asserted for 1PCLK), or
Level (asserted until the error flags are cleared).
The default is Pulse.
♦
SERR# (System Error)Enable
This is the master enable bit for SERR# generation.
The default is
disabled.