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Chapter 4
BIOS Configuration
is Enabled.
SDRAM RAS to CAS Delay
This field lets you insert a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Fast gives
faster performance; and Slow gives more stable performance. This field applies
only when synchronous DRAM is installed in the system.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the DRAM
may fail to retain data. Fast gives faster performance; and Slow gives more
stable performance. This field applies only when synchronous DRAM is
installed in the system.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. Do not reset this field from the default
value specified by the system designer.
DRAM ECC/Parity Select
Select Parity, ECC (error-correcting code), or Disabled, depending on the type
of DRAM installed in your system.
CPU-To-PCI IDE Posting
Select Enabled to post write cycles from the CPU to the PCI IDE interface. IDE
accesses are posted in the CPU to PCI buffers, for cycle optimization.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system performance. However, if any program writes to this
memory area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program writes
to this memory area, a memory access error may result.
Video RAM Cacheable
Selecting Enabled allows caching of the video memory, resulting in better
video performance.
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