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4 Receiver Description
4.1 Overview
The
ANTARIS
®
4
GPS
Module
is
a
self-contained
receiver
for
the
Global
Positioning
System
(GPS).
The
complete
signal
processing
chain
from
antenna
input
to
serial
output
is
contained
within
a
single
component.
The
height
of
3mm
(~120mil)
and
small
size
makes
it
the
ideal
GPS
solution
for
applications
with
stringent
space
requirements.
This
type
of
package
makes
expensive
RF
cabling
obsolete.
The
RF
input
is
available
directly
on
a
pin,
the
ANTARIS
®
4
GPS
Module
is
SMT
solderable
and
can
be
handled
by
standard
pick
and
place
equipment.
The
ANTARIS
®
4
GPS
Receiver
provides
up
to
two
serial
ports,
which
can
handle
NMEA,
UBX
proprietary
data
format
and
differential
GPS
correction
data
(RTCM)
and
a
USB
device
port
(only
LEA-4x
and
NEO-4x
modules)
4.1.1 Block
Schematic
The
ANTARIS
®
4
GPS
receiver
is
divided
into
two
distinct,
separately
shielded
sections.
The
smaller
section
is
the
RF-
Section,
the
larger
section
contains
the
baseband.
The
RF
section
contains
the
low
noise
amplifier
(LNA)
ATR0610,
the
SAW
bandpass
filter,
the
RF-IC
ATR0601
and
the
GPS
crystal.
The
ATR0601
uses
a
single
IF
sub-sampling
scheme
with
an
analogue
IF
of
96.764
MHz,
a
sampling
frequency
of
23.104
MHz,
and
a
resulting
digital
IF
of
4.348
MHz.
The
baseband
section
contains
the
digital
circuitry
comprised
of
the
ATR062x
baseband
processor,
the
RTC
crystal
and
additional
elements
as
such
optional
FLASH
memory
where
specified.
d
by
a
number
of
digital
signals:
Control
signals
from
the
digital
part
switch
The
two sections
are
connecte
between
different
power
states
of
the
RF
section.
The
23.104
MHz
clock
is
supplied
to
the
digital
part
as
well
as
the
1.5
bit
quantized
IF
signal.
Another
status
signal
reports
the
status
of
the
antenna
bias
input
to
the
baseband
processor.
Finally,
after
rigorous
filtering,
power
is
supplied
from
the
digital
part
to
the
RF
part.
ATR0601
ATR062x
Battery
backed
RAM (
BBR
)
4 kB
[32 Bit]
RESET
ARM7
CPU
SRAM
128 kB
[32 Bit]
ROM
288 kB
[32 Bit]
GPS
Channels
FLASH
Memory
min.
4Mbit
[16 Bit]
32.768 kHz
Data Bus
Di
g
it
a
l IF
&
Clo
c
k
1.8V
LDO
VBAT
LDO
RTC
23.104 MHz
I/Os
XTO
VCC
GND
Boot_int
RxD1
TxD1
TxD2
RxD2
R
V_ant
P0
RF_ON
SLEEP_N
GND
SAW-Filter
A
D
I/Os
Address Bus
F_in
GND
AADET_N
VBAT
Reset_N (O.D. @ 1.8 V)
P15
ATR0610
(optional)
GPIO Pi
GPSMODE Pins
EXTINT0
ns or
USB
Figure 48: Hardware Block Schematic
GPS
Modules
-
System
Integration
Manual
(SIM)
(incl.
Reference
Design)
Receiver
Description
GPS.G4-MS4-05007-A1
Page 59
