LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
Design-in
Page 108 of 148
2.6.3.2
Guidelines for HSIC layout design
HSIC lines require accurate layout design to achieve reliable signaling at high speed data rate (up to 480 Mb/s),
as supported by the HSIC serial interface: signal integrity may be degraded if PCB layout is not optimal, especially
when the HSIC lines are very long.
The characteristic impedance of the
HSIC_DATA
and
HSIC_STRB
lines has to be as close as possible to 50
, as
specified by the
High-Speed Inter-Chip USB Electrical Specification Version 1.0
Use the following general routing guidelines to minimize signal quality problems:
Route
HSIC_DATA
and
HSIC_STRB
lines as short as possible.
HSIC interface is only recommended for intra-board interconnect. The connection should be point-to-point.
Connectors and cables are not recommended.
HSIC_DATA
and
HSIC_STRB
lines must be matched in length to within 10 mils.
Ensure the characteristic impedance of
HSIC_DATA
and
HSIC_STRB
lines is as close as possible to 50
.
HSIC_DATA
and
HSIC_STRB
signals are not differential signals and should not be routed as such.
Consider design rules for
HSIC_DATA
and
HSIC_STRB
lines similar to RF transmission lines, routing them as
micro-strips (conducting strips separated from ground plane by dielectric material) or striplines (flat strips of
metal sandwiched between two parallel ground planes within a dielectric material).
Avoid any stubs, abrupt change of layout, and route on clear PCB area.
Avoid coupling with any RF line or sensitive analog inputs, since the signals can cause the radiation of some
harmonics of the digital data frequency.
Figure 40 and Figure 41 provide two examples of proper 50
coplanar waveguide designs. The first example of
RF transmission line can be implemented in case of 4-layer PCB stack-up herein described, and the second
example of RF transmission line can be implemented in case of 2-layer PCB stack-up herein described.
If the two examples do not match the application PCB layup, the 50
characteristic impedance calculation can
be made using the HFSS commercial finite element method solver for electromagnetic structures from Ansys
Corporation, or using freeware tools like AppCAD from Agilent (www.agilent.com) or TXLine from Applied
Wave Research (www.mwoffice.com), taking care of the approximation formulas used by the tools for the
impedance computation.
To achieve a 50
characteristic impedance, the width of the transmission line must be chosen depending on:
the thickness of the transmission line itself (e.g. 35 µm in the example of Figure 40 and Figure 41)
the thickness of the dielectric material between the top layer (where the transmission line is routed) and the
inner closer layer implementing the ground plane (e.g. 270 µm in Figure 40, 1510 µm in Figure 41)
the dielectric constant of the dielectric material (e.g. dielectric constant of the FR-4 dielectric material in
Figure 40 and Figure 41)
the gap from the transmission line to the adjacent ground plane on the same layer of the transmission line
(e.g. 500 µm in Figure 40, 400 µm in Figure 41)
If the distance between the transmission line and the adjacent GND area (on the same layer) does not exceed 5
times the track width of the micro strip, use the “Coplanar Waveguide” model for the 50
calculation.
