LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
Design-in
Page 124 of 148
2.15
Design-in checklist
This section provides a design-in checklist.
2.15.1
Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at
VCC
pin within the operating range limits.
DC supply must be capable of supporting both the highest peak and the highest averaged current
consumption values in connected-mode, as specified in the
LARA-R2 series
Data Sheet
VCC
voltage supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors,
in particular if the application device integrates an internal antenna.
Do not apply loads which might exceed the limit for maximum available current from
V_INT
supply.
Check that voltage level of any connected pin does not exceed the relative operating range.
Provide accessible test points directly connected to the following pins of the LARA-R2 series modules:
V_INT
,
PWR_ON
and
RESET_N
for diagnostic purpose.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested pF capacitors on each SIM signal and low capacitance ESD protections if accessible.
Check UART signals direction, as the modules’ signal names follow
ITU-T V.24 Recommendation
Provide accessible test points directly connected to all the UART pins of the LARA-R2 series modules
(
TXD
,
RXD
,
DTR
,
DCD
) for diagnostic purpose, in particular providing a 0
series jumper on each line
to detach each UART pin of the module from the DTE application processor.
Capacitance and series resistance must be limited on each high speed line of the USB interface.
If the USB is not used, provide accessible test points directly connected to the USB interface (
VUSB_DET
,
USB_D+
and
USB_D-
pins).
Capacitance and series resistance must be limited on each high speed line of the HSIC interface.
Consider providing appropriate low value series damping resistors on SDIO lines to avoid reflections.
Add a proper pull-up resistor (e.g. 4.7 k
) to
V_INT
or another proper 1.8 V supply on each DDC (I
2
C)
interface line, if the interface is used.
Check the digital audio interface specifications to connect a proper external audio device.
Capacitance and series resistance must be limited on master clock output line and each I
2
S interface line
Consider passive filtering parts on each used analog audio line.
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k
resistor on
the board in series to the GPIO when those are used to drive LEDs.
Provide proper precautions for ESD immunity as required on the application board.
Do not apply voltage to any generic digital interface pin of LARA-R2 series modules before the switch-on
of the generic digital interface supply source (
V_INT
).
All unused pins of LARA-R2 series modules can be left unconnected except the
RSVD
pin number
33
,
which must be connected to GND.
