LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
Design-in
Page 64 of 148
2
Design-in
2.1
Overview
For an optimal integration of LARA-R2 series modules in the final application board follow the design guidelines
stated in this section.
Every application circuit must be properly designed to guarantee the correct functionality of the related interface,
however a number of points require higher attention during the design of the application device.
The following list provides a ranking of importance in the application design, starting from the highest relevance:
1.
Module antenna connection:
ANT1
,
ANT2
and
ANT_DET
pins.
Antenna circuit directly affects the RF compliance of the device integrating a LARA-R2 series module with
the applicable certification schemes. Very carefully follow the suggestions provided in section 2.4 for
schematic and layout design.
2.
Module supply:
VCC
and
GND
pins.
The supply circuit affects the RF compliance of the device integrating a LARA-R2 series module with
applicable certification schemes as well as antenna circuit design. Very carefully follow the suggestions
provided in section 2.2.1 for schematic and layout design.
3.
USB interface:
USB_D+
,
USB_D-
and
VUSB_DET
pins.
Accurate design is required to guarantee USB 2.0 high-speed interface functionality. Carefully follow the
suggestions provided in the related section 2.6.1 for schematic and layout design.
4.
SIM interface:
VSIM
,
SIM_CLK
,
SIM_IO
,
SIM_RST
,
SIM_DET
pins.
Accurate design is required to guarantee SIM card functionality and compliance with applicable
conformance standards, reducing also the risk of RF coupling. Carefully follow the suggestions provided in
section 2.5 for schematic and layout design.
5.
HSIC interface:
HSIC_DATA
,
HSIC_STRB
pins.
Accurate design is required to guarantee HSIC interface functionality. Carefully follow the suggestions
provided in the relative section 2.6.3 for schematic and layout design.
6.
SDIO interface:
SDIO_D0
,
SDIO_D1
,
SDIO_D2
,
SDIO_D3
,
SDIO_CLK
,
SDIO_CMD
pins.
Accurate design is required to guarantee SDIO interface functionality. Carefully follow the suggestions
provided in the relative section 2.6.5 for schematic and layout design.
7.
System functions:
RESET_N
,
PWR_ON
pins.
Accurate design is required to guarantee that the voltage level is well defined during operation. Carefully
follow the suggestions provided in section 2.3 for schematic and layout design.
8.
Other digital interfaces: UART, I
2
C, I
2
S, Host Select, GPIOs, and Reserved pins.
Accurate design is required to guarantee proper functionality and reduce the risk of digital data frequency
harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.4, 2.7.1, 2.3.3, 2.8 and 2.9 for
schematic and layout design.
9.
Other supplies: the
V_BCKP
RTC supply input/output and the
V_INT
digital interfaces supply output.
Accurate design is required to guarantee proper functionality. Follow the suggestions provided in sections
2.2.2 and 2.2.3 for schematic and layout design.
It is recommended to follow the specific design guidelines provided by each manufacturer of any external
part selected for the application board integrating the u-blox cellular modules.
