LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
Design-in
Page 118 of 148
2.8
General Purpose Input/Output (GPIO)
2.8.1.1
Guidelines for GPIO circuit design
A typical usage of LARA-R2 series modules’ GPIOs can be the following:
Network indication provided over
GPIO1
pin (see Figure 64 / Table 48 below)
GNSS supply enable function provided by the
GPIO2
pin (see section 2.6.4)
GNSS Tx data ready function provided by the
GPIO3
pin (see section 2.6.4)
GNSS RTC sharing function provided by the
GPIO4
pin (see section 2.6.4)
SIM card detection provided over
GPIO5
pin (see Figure 46 / Table 37 in section 2.5)
LARA-R2 series
GPIO1
R1
R3
3V8
Network Indicator
R2
16
DL1
T1
Figure 64: Application circuit for network indication provided over GPIO1
Reference
Description
Part Number - Manufacturer
R1
10 k
Resistor 0402 5% 0.1 W
Various manufacturers
R2
47 k
Resistor 0402 5% 0.1 W
Various manufacturers
R3
820
Resistor 0402 5% 0.1 W
Various manufacturers
DL1
LED Red SMT 0603
LTST-C190KRKT - Lite-on Technology Corporation
T1
NPN BJT Transistor
BC847 - Infineon
Table 48: Components for network indication application circuit
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k
Ω
resistor on the
board in series to the GPIO of LARA-R2 series modules.
Do not apply voltage to any GPIO of the module before the switch-on of the GPIOs supply (
V_INT
), to
avoid latch-up of circuits and allow a proper module boot. If the external signals connected to the module
cannot be tri-stated or set low, insert a multi channel digital switch (e.g. TI SN74CB3Q16244, TS5A3159,
TS5A63157) between the two-circuit connections and set to high impedance before
V_INT
switch-on.
ESD sensitivity rating of the GPIO pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
If the GPIO pins are not used, they can be left unconnected on the application board.
2.8.1.2
Guidelines for GPIO layout design
The general purpose input/output pins are generally not critical for layout.
