LARA-R2 series - System Integration Manual
UBX-16010573 - R02
Objective Specification
System description
Page 53 of 148
1.11
Clock output
LARA-R2 series modules provide master digital clock output function on
GPIO6
pin, which can be configured to
provide a 13 MHz or 26 MHz square wave. This is mainly designed to feed the master clock input of an external
audio codec, as the clock output can be configured in “Audio dependent” mode (generating the square wave
only when the audio path is active), or in “Continuous” mode.
For more details see the
u-blox AT Commands Manual
[2], +UMCLK AT command.
1.12
General Purpose Input/Output (GPIO)
LARA-R2 series modules include 9 pins (
GPIO1
-
GPIO5
,
I2S_TXD
,
I2S_RXD
,
I2S_CLK
,
I2S_WA
) which can be
configured as General Purpose Input/Output or to provide custom functions via u-blox AT commands (for more
details see the
u-blox AT Commands Manual
[2], +UGPIOC, +UGPIOR, +UGPIOW AT commands), as summarized
Function
Description
Default GPIO
Configurable GPIOs
Network status
indication
Network status: registered home network, registered
roaming, data transmission, no service
--
GPIO1-GPIO4
GNSS supply enable
14
Enable/disable the supply of u-blox GNSS receiver
connected to the cellular module
--
GPIO1-GPIO4
GNSS data ready
Sense when u-blox GNSS receiver connected to the
module is ready for sending data by the DDC (I
2
C)
--
GPIO3
GNSS RTC sharing
RTC synchronization signal to the u-blox GNSS receiver
connected to the cellular module
--
GPIO4
SIM card detection
External SIM card physical presence detection
GPIO5
GPIO5
SIM card hot
insertion/removal
Enable / disable SIM interface upon detection of external
SIM card physical insertion / removal
--
GPIO5
I
2
S digital audio
interface
15
I
2
S digital audio interface
I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
I2S_RXD, I2S_TXD,
I2S_CLK, I2S_WA
Wi-Fi control
Control of an external Wi-Fi chip or module
--
--
General purpose input
Input to sense high or low digital level
--
All
General purpose output
Output to set the high or the low digital level
GPIO4
All
Pin disabled
Tri-state with an internal active pull-down enabled
GPIO1-GPIO3
All
Table 12: LARA-R2 series GPIO custom functions configuration
1.13
Reserved pins (RSVD)
LARA-R2 series modules have pins reserved for future use, named
RSVD
: they can all be left unconnected on the
application board, except
the
RSVD
pin number
33
that must be externally connected to ground
14
Not supported by “02” product versions.
15
Not supported by LARA-R204 module “02” product version.