NINA-W1 series - System Integration Manual
UBX-17005730 - R07
Design-in
Page 34 of 47
Figure 25: NINA-W102 or NINA-W132 with internal antenna
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Take care while handling the EVK-NINA-W102/W132/W152. Applying force to the module might
damage the internal antenna.
3.4
Data communication interfaces
3.4.1
Asynchronous serial interface (UART) design
The layout of the UART bus should be done so that noise injection and cross talk are avoided. It is
recommended to use the hardware flow control with RTS/CTS to prevent temporary UART buffer
overrun.
•
If CTS is 1, then the Host/Host Controller is allowed to send.
•
If CTS is 0, then the Host/Host Controller is not allowed to send.
3.4.2
Ethernet (RMII+SMI)
It is recommended to route all signals in the RMII bus with the same length and have appropriate
grounding in the surrounding layers; total bus length should also be minimized. The layout of the
RMII bus should be done so that crosstalk with other parts of the circuit is minimized providing
adequate isolation between the signals, the clock and the surrounding busses/traces.
Termination resistors are recommended on the RX and TX lines of the RMII bus.
Pull-up resistor is required for MDIO.
The General High Speed layout guidelines in section 3.5 apply for the RMII and the SMI bus.
3.5
General High Speed layout guidelines
These general design guidelines are considered as best practices and are valid for any bus present in
the NINA-W1 series modules; the designer should prioritize the layout of higher speed busses. Low
frequency signals are generally not critical for layout.
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One exception is represented by High Impedance traces (such as signals driven by weak pull
resistors) that may be affected by crosstalk. For those traces, a supplementary isolation of 4w
from other busses is recommended.
3.5.1
General considerations for schematic design and PCB floor-planning
•
Verify which signal bus requires termination and add series resistor terminations to the
schematics.
