NORA-W10 series - System integration manual
UBX-22005601 - R04
Design-in
Page 25 of 56
C1-Public
3.3
Data communication interfaces
3.3.1
Asynchronous serial interface (UART) design
The layout of the UART bus should be done so that noise injection and cross talk are avoided. It is
advisable to use the hardware flow control with RTS/CTS to prevent temporary UART buffer overrun.
The flow control signals
RTS/CTS
are active low. Consequently, 0 (ON state =low level) allows the
UART to transmit.
•
CTS
is an input to the NORA-W10 module. If the host sets this input to 0 (ON state = low level) the
module can transmit.
•
RTS
is an output off the NORA-W10 module. The module sets the output to 0 (ON state = low level)
when it is ready to receive transmission.
3.4
General high-speed layout guidelines
These guidelines describe the best schematic and layout practices for integrating the module on a
host PCB. Designers should prioritize the layout of higher speed busses. Low frequency signals,
other than those with high-impedance traces, are generally not layout critical.
⚠
Low frequency signals with high-impedance traces (such as signals driven by weak pull resistors)
may be affected by crosstalk. For these high-impedance traces, a supplementary isolation of 4*W
from other busses is recommended.
3.4.1
Considerations for schematic design and PCB floor-planning
•
Verify which signal bus requires termination and add series resistor terminations to the
schematics.
•
Carefully consider the placement of the module with respect to antenna position and host
processor.
•
Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning.
•
Verify that the power supply design and power sequence are compliant with the specification of
NORA-W10 series module.
3.4.2
Component placement
•
Accessory parts like bypass capacitors should be placed as close as possible to the module to
improve filtering capability, prioritizing the placement of the smallest size capacitor close to
module pads.
•
Do not place components close to the antenna area. Follow the recommendations of the antenna
manufacturer to determine distance of the antenna in relation to other parts of the system.
Designers should also maximize the distance of the antenna to High-frequency busses, like DDRs
and related components. Alternatively, consider an optional metal shield to reduce interference
that might otherwise be picked up by the antenna and subsequently reduce module sensitivity.
•
An optimized module placement allows better RF performance. For more information about the
module placement and other antenna considerations, see also
3.4.3
Layout and manufacturing
•
Avoid stubs on high-speed signals. Test points or component pads should be placed over the PCB
trace.
•
Verify the recommended maximum signal skew for differential pairs and length matching of buses.
•
Minimize the routing length; longer traces degrade signal performance. Ensure that maximum
allowable length for high-speed busses is not exceeded.
