NORA-W10 series - System integration manual
UBX-22005601 - R04
Design-in
Page 26 of 56
C1-Public
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Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for
proper stack-up definition.
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RF, analog, and digital sections should have dedicated and clearly separated areas on the board.
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No digital routing is allowed in the GND reference plane area of RF traces (ANT pins and Antenna).
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Designers are strongly recommended to avoid digital routing beneath all layers of RF traces.
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Ground cuts or separation are not allowed below the module.
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As a first priority, minimize the length of the RF traces. Then, minimize bus length to reduce
potential EMI issues related to the radiation of digital busses.
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All traces (Including low speed or DC traces) must couple with a reference plane (GND or power).
High-speed busses should be referenced to the ground plane. If designers need to change the
ground reference, some capacitors should be added and an adequate number of GND vias must
be added in the area of transition. This facilitates a low-impedance path between the two GND
layers for the return current.
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Trace routing should maintain a distance that is greater than 3*W from the edge of the ground
plane routing.
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Do not route power planes or traces in loops.
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Route the power traces through both the bypass capacitor and bulk capacitor before connecting
to the module’s pin.
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Power planes should maintain a safe distance from the edge of the PCB. The distance must be
sufficient to route a ground ring around the PCB, and the ground ring must then be stitched to
other layers through vias.
3.5
Module footprint and paste mask
Figure 9: NORA-W10 mechanical outline
