NORA-W30 series - System integration manual
UBX-22021119 - R02
Module overview
Page 10 of 52
C1-Public
1.4
Pin multiplexing
Only certain functions may be enabled at one time.
describes the pin multiplexing options.
Table 3: Pin multiplexing table
UBXDOC-39674697-1341 C2-Restricted
NORA-W30 GPIO pin-mux
Port Name
Bootstrap
Internal pull
Module pull FUNC_ID0
FUNC_ID1
FUNC_ID2
FUNC_ID3
FUNC_ID4
FUNC_ID5
FUNC_ID6
FUNC_ID7
FUNC_ID8
FUNC_ID9
FUNC_ID10
FUNC_ID11
FUNC_ID12
FUNC_ID1
4
FUNC_ID1
5
FUNC_ID18
FUNC_ID20
FUNC_ID2
1
FUNC_ID22
FUNC_ID23
FUNC_ID28
FUNC_ID2
9
FUNC_ID30
FUNC_ID3
1
default
RTK9720DF
pull
gpio
UART DATA
LOG UART
RTS/CTS
SPI
RTC
IR
SPI f lash
I2C
SDIO
HS pwm
LP pwm
SWD
I2S/DMIC
USB
HEADPHO
NE
Wif i only
RFE control
Ext. BT
Combo
RFE
control
HS timer trig
Debug Port
Ext32K
key scan
ROW
key scan
COL
WAKEUP
default function
shutdown3
3 group
PA[7]
uart_download
Internal UP
50 kΩ pull-up
PA[7]
UART_LOG_TXD
ANT_SEL_P
PA[7]
5
PA[8]
Internal UP
PA[8]
UART_LOG_RXD
ANT_SEL_N
PA[8]
5
PA[12]
icfg0
PA[12]
LP_UART_TXD
SPI1_MOSI
HS_PWM0
LP_PWM0
I2S_MCLK
ANT_SEL_N
GRANT_BT
EN_EXLNA
KEY_ROW0
LGPIO[0]
PA[12]
2
PA[13]
icfg1
EfusePullCtrl0
PA[13]
LP_UART_RXD
SPI1_MISO
HS_PWM1
LP_PWM1
I2S_SD_TX1
ANT_SEL_P
GRANT_BT_N
EN_EXPA
KEY_ROW1
LGPIO[1]
PA[13]
2
PA[14]
icfg2
PA[14]
LP_UART_RTS
SPI1_CLK
I2S_SD_TX2
ANT_SEL_N
BT_DIS
RTC_OUT
KEY_ROW2
LGPIO[2]
PA[14]
2
PA[15]
icfg3
EfusePullCtrl1
PA[15]
LP_UART_CTS
SPI1_CS
ANT_SEL_P
BT_WAKE_HOST
RTC EXT_32K KEY_ROW3 KEY_COL6
LGPIO[3]
PA[15]
2
PA[25]
EfusePullCtrl2
PA[25]
LP_UART_RXD
HS_USI_SPI_MOSI
IR_TX
LP_I2C_SCL
HS_PWM4
LP_PWM4
HSDM
MBOX_I2C_INT
wlmac_dbggpio[0]
KEY_COL1
PA[25]
2
PA[26]
PA[26]
LP_UART_TXD
HS_USI_SPI_MISO
IR_RX
LP_I2C_SDA
HS_PWM5
LP_PWM5
HSDP
BT_ACT
wlmac_dbggpio[1]
KEY_COL0
PA[26]
2
PA[27]
normal_mode_sel
Internal UP
50 kΩ pull-up
PA[27]
LP_UART_RTS
SWD_DATA
WLAN_ACT
wlmac_dbggpio[2]
SWD_DATA when efuse
enable
5
PA[28]
EfusePullCtrl3
PA[28]
LP_UART_CTS
HS_USI_SPI_CS
HS_PWM6
LP_PWM0
RREF
BT_CK
wlmac_dbggpio[3]
PA[28]
5
PA[30]
sps_sel
External UP
10 kΩ pull-up
PA[30]
HS_USI_SPI_CLK
HS_PWM7
LP_PWM1
EXTBT_UART_RTS
wlmac_dbggpio[4]
PA[30]
5
PB[1]
EfusePullCtrl4
PB[1]
LP_UART_TXD
DMIC_CLK
ANT_SEL_N
BT_STE
EN_EXLNA HS_TIM4_TRIG wlmac_dbggpio[5]
PB[1]
5
PB[2]
PB[2]
LP_UART_RXD
DMIC_DATA
ANT_SEL_P
PCM_CLK
EN_EXPA HS_TIM5_TRIG wlmac_dbggpio[6]
PB[2]
5
PB[3]
PB[3]
SWD_CLK
PCM_SYNC
wlmac_dbggpio[7]
SWD_CLK when efuse
enable
5
PB[18]
PB[18]
HS_UART0_RXD
HS_USI_UART_RTS
SPI0_MOSI
SPI_CS
SD_D2
HS_PWM10
LP_PWM4
SWD_CLK
SWD_CLK when efuse
enable, or SD_D2 when
efuse enable SDIO
1
PB[19]
EfusePullCtrl6
PB[19]
HS_UART0_TXD
HS_USI_UART_CTS
SPI0_MISO
SPI_DATA1
SD_D3
HS_PWM11
LP_PWM5
SWD_DATA
I2S_SD_TX0
SWD_DATA when efuse
enable,or SD_D3 when
efuse enable SDIO
1
PB[20]
PB[20]
HS_USI_UART_TXD
HS_UART0_CTS
SPI0_CLK
SPI_DATA0
HS_USI_I2C_SCL
SD_CMD
HS_PWM12
LP_PWM0
I2S_CLK
SD_CMD when efuse
enable SDIO
1
PB[21]
PB[21]
HS_USI_UART_RXD
HS_UART0_RTS
SPI0_CS
SPI_CLK
HS_USI_I2C_SDA
SD_CLK
HS_PWM13
LP_PWM1
I2S_WS
QDEC_IDX
SD_CLK when efuse
enable SDIO
1
PB[22]
EfusePullCtrl7
PB[22]
LP_TIM4_TRIG
IR_RX
SPI_DATA3
SD_D0
HS_PWM14
LP_PWM2
I2S_SD_RX
QDEC_PHB
EXTBT_UART_CTS
wlmac_dbggpio[8]
SD_D0 when efuse enable
SDIO
1
PB[23]
PB[23]
LP_TIM5_TRIG
IR_TX
SPI_DATA2
SD_D1
HS_PWM15
LP_PWM3
I2S_MCLK
QDEC_PHA
EXT_32K
wlmac_dbggpio[9]
SD_D1 when efuse enable
SDIO
1