EVK-NINA-B4 - User guide
UBX-19054587 - R03
Interfaces and peripherals
Page 29 of 38
C1 - Public
Figure 18: Additional interfaces that require some soldering before use
Connector
annotation
Pin
number
Schematic net name
nRF52 pin Description
U10
1
SPI_CS/GPIO_51
P1.08
Chip select input signal, active low
2
SPI_MISO/GPIO_48
P0.21
MISO in single SPI mode, or data I/O signal in dual/quad mode
3
GPIO_49
P0.22
4
GND
GND
Ground
5
SPI_MOSI/GPIO_50
P0.20
MOSI in single SPI mode, or data I/O signal in dual/quad mode
6
SPI_CLK/GPIO_52
P0.08
Chip clock input signal, up to 32 MHz supported
7
GPIO_47
P0.06
8
VDD_IO
-
Supply net for LEDs and peripherals connected directly to the
NINA module. Supply for the external memory chip.
J20
1
MCU_TXD
-
Interface MCU data output signal
2
MCU_RXD
-
Interface MCU data input signal
3
MCU_RTS
-
Interface MCU flow control output signal
4
MCU_CTS
-
Interface MCU flow control input signal
5
GND
GND
Ground
J21
1
VDD_IO
-
Supply net for LEDs and peripherals connected directly to the
NINA module. Supply for the external memory chip.
2
SWDIO
SWDIO
Serial Wire Debug data I/O signal
3
GND
GND
Ground
4
SWDCLK
SWDCLK
Serial Wire Debug clock signal
5
GND
GND
Ground
6
TRACE_D0/SWO/
GPIO_8
P1.00
Serial trace data signal / Parallell trace data signal
7
N/C
-
Not connected
8
N/C
-
Not connected
9
GND
GND
Ground
10
RESET_N
P0.18
NINA reset signal, active low
J20
UART
U10
C54
Flash Memory
VDD_IO
GPIO_47
SPI_CLK
SPI_MOSI
U10
GND
CTS
RTS
RXD
TXD
1
J20
5
3
4
6
5
8
7
T
RA
CE_
D
1
T
RA
CE_
D
2
T
RA
CE_
D
0
T
RA
CE_
D
3
T
RA
CE_
CLK
G
ND
G
ND
G
ND
N/
C
N/
C
J21
T
RA
CE_
D
0
N/
C
S
WD
CLK
RE
S
ET
_N
SW
D
IO
G
ND
N/
C
G
ND
G
ND
V
D
D
_I
O
19
20
1
2
Additional Interfaces
Trace
J21
GPIO_49
SPI_MISO
GND
SPI_CS
External Flash
Debug and Trace
UART
1
2