LENA-R8 series - System integration manual
UBX-22015376 - R02
Design-in
Page 76 of 116
C1-Public
Providing 2 UARTs with TXD, RXD, RTS and CTS lines only
The auxiliary secondary UART interface is disabled by default, and it can be enabled by dedicated AT
command (see the u-blox AT commands manual
, +USIO AT command) as alternative function of
the
DTR
,
DSR
,
DCD
and
RI
pins of the main primary UART interface, in mutually exclusive way.
If RS-232 compatible signal levels are needed, two Maxim MAX13234E voltage level translators can
be used. These chips translate voltage levels from 1.8 V (module side) to the RS-232 standard.
If a 1.8 V application processor is used, the circuit should be implemented as described in
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
TxD
RxD
RTS
CTS
GND
LENA-R8 series
(1.8V DCE)
12
TXD
(UART data input)
9
DTR
(AUX UART data input)
13
RXD
(UART data ouput)
10
RTS
(UART flow ctrl input)
11
CTS
(UART flow ctrl output)
8
DCD
(AUX UART data ouput)
6
DSR
(AUX UART flow ctrl input)
7
RI
(AUX UART flow ctrl output)
GND
0
Ω
TP
0
Ω
TP
UART1
UART2
0
Ω
TP
0
Ω
TP
100
Ω
Figure 53: 2 UART interfaces application circuit with HW flow control in DTE/DCE serial communications (1.8 V DTE)
If a 3.0 V application processor (DTE) is used, then it is recommended to connect the 1.8 V UART
interfaces of the module (DCE) by means of appropriate unidirectional voltage translators using the
module
V_INT
output as 1.8 V supply for the voltage translators on the module side, as in
4
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
RTS
CTS
TxD
RxD
RTS
CTS
GND
LENA-R8 series
(1.8V DCE)
12
TXD
(UART data input)
9
DTR
(AUX UART data input)
13
RXD
(UART data output)
10
RTS
(UART flow ctrl input)
11
CTS
(UART flow ctrl output)
8
DCD
(AUX UART data output)
6
DSR
(AUX UART flow ctrl input)
7
RI
(AUX UART flow ctrl output)
GND
1V8
B1
A1
GND
U1
B3
A3
VCCB
VCCA
Unidirectional
voltage translator
C1
C2
3V0
DIR3
DIR2
OE
DIR1
VCC
B2
A2
B4
A4
DIR4
1V8
B1
A1
GND
U2
B3
A3
VCCB
VCCA
Unidirectional
voltage translator
C3
C4
3V0
DIR3
DIR1
OE
B2
A2
B4
A4
DIR4
DIR2
0
Ω
TP
0
Ω
TP
TP
UART1
UART2
0
Ω
TP
0
Ω
TP
100
Ω
Figure 54: 2 UART interfaces application circuit with HW flow control in DTE/DCE serial communications (3.0 V DTE)
Reference
Description
Part number - Manufacturer
C1, C2, C3, C4
100 nF Capacitor Ceramic
Various Manufacturers
U1, U2
Unidirectional voltage translator
SN74AVC4T774
8
- Texas Instruments
Table 39: Components for 2 UARTs application circuit with HW flow control in DTE/DCE serial communications (3.0 V DTE)
☞
The
DSR
and
DCD
pins toggle as output for ~600 ms during the boot of the module cellular system.
The
DSR
and
DCD
pins are also set as output during the firmware update over the USB interface.
Proper precaution must be taken for the
DSR
line if it is connected to an output of an external
device, or if it is grounded. Provide for example an external 100 Ohm series resistor to detach the
output of the module from the output of the external device or the ground.
8
Voltage translator providing partial power down feature, so the 3 V supply can be also ramped up before
V_INT
1.8 V supply
