NEO-D9S - Integration manual
Figure 6: I2C random read access
If the second form, "current address" is used, an address pointer in the receiver is used to determine
which register to read. This address pointer will increment after each read unless it is already
pointing at register 0xFF, the highest addressable register, in which case it remains unaltered.
The initial value of this address pointer at start-up is 0xFF, so by default all current address reads
will repeatedly read register 0xFF and receive the next byte of message data (or 0xFF if no message
data is waiting).
Figure 7: I2C current address read access
3.2.2.3 Write access
The receiver does not provide any write access except for writing UBX and NMEA messages to the
receiver, such as configuration or aiding data. Therefore, the register set mentioned in the section
Following the start condition from the master, the 7-bit device address and the RW bit (which is a
logic low for write access) are clocked onto the bus by the master transmitter. The receiver answers
with an acknowledge (logic low) to indicate that it is responsible for the given address.
The master can write 2 to N bytes to the receiver, generating a stop condition after the last byte
being written. The number of data bytes must be at least 2 to properly distinguish from the write
access to set the address counter in random read accesses.
UBX-19026111 - R07
3 Receiver functionality
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