SARA-G450 - System integration manual
UBX-18046432 - R08
Design-in
Page 97 of 143
C1-Public
Additional considerations
If a 3.0 V application processor (DTE) is used and module (DCE) generic digital interfaces are
configured to operate at 1.8 V (V_INT = 1.8 V, if VSEL pin is connected to GND; see
), the voltage
scaling from any 3.0 V output of the application processor (DTE) to the corresponding 1.8 V input of
the module (DCE) can be implemented, as an alternative low-cost solution, by means of an appropriate
voltage divider. Consider the value of the pull-up integrated at the input of the module (DCE) for the
correct selection of the voltage divider resistance values.
Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding
3.0 V input of the application processor (DTE) can be implemented by means of an appropriate
low-cost non-inverting buffer with open drain output. The non-inverting buffer should be supplied by
the V_INT supply output of the cellular module. Consider the value of the pull-up integrated at each
input of the DTE (if any) and the baud rate required by the application for the appropriate selection of
the resistance value for the external pull-up biased by the application processor supply rail.
☞
It is highly recommended to provide on the application board a directly accessible Test-Point for
the TXD, RXD, RTS, CTS pins of the module for execution of firmware upgrades and for diagnostic
purposes: provide a Test-Point on each line to accommodate the access and provide a 0
Ω
series
resistor on each line to detach the module pins from any other connected device.
☞
Any external signal connected to the UART interface must be tri-stated or set low when the
module is in power-off mode and during the module power-on sequence (at least until the settling
of the V_INT supply output of the module to the configured 1.8 / 3.0 value), to avoid latch-up of
circuits and allow a clean boot of the module. If the external signals connected to the cellular
module cannot be tri-stated or set low, insert a multi-channel digital switch (e.g. Texas
Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections
and set to high impedance during the module power-on sequence.
☞
The ESD sensitivity rating of UART interface pins is 1 kV (Human Body Model according to
JESD22-A114). A higher protection level could be required if the lines are externally accessible on
the application board. This higher protection level can be achieved by mounting an ESD protection
(e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points.
2.6.1.2
Guidelines for UART layout design
The UART serial interface requires the same consideration regarding electromagnetic interference as
any other digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog
inputs, since the signals can cause the radiation of some harmonics of the digital data frequency.