SARA-G450 - System integration manual
UBX-18046432 - R08
Design-in
Page 100 of 143
C1-Public
2.6.3.2
Guidelines for FT UART layout design
The additional FT UART serial interface requires the same consideration regarding electromagnetic
interference as any other digital interface. Keep the traces short and avoid coupling with RF line or
sensitive analog inputs, since the signals can cause the radiation of some harmonics of the digital
data frequency.
2.6.4
DDC (I2C) interface
☞
DDC (I2C) interface is not supported by the “00” product version. This interface should be left
unconnected and should not be driven by external devices.
2.6.4.1
Guidelines for DDC (I2C) circuit design
General considerations
The DDC I2C-bus master interface of SARA-G450 cellular modules can be used to communicate with
u-blox GNSS receivers. Besides the general considerations detailed below, see the following parts of
this section for specific guidelines for the connection to u-blox GNSS receivers.
To be compliant to the I2C-bus specifications, the module bus interface pins are open drain output
and pull-up resistors must be mounted externally. Resistor values must conform to the I2C bus
specifications
: for example, 4.7 k
Ω
resistors can be commonly used.
☞
Connect the external DDC (I2C) pull-ups to the V_INT supply source, or another supply source
enabled after V_INT (e.g., as the GNSS supply present in
circuits), as any external signal connected to the DDC (I2C) interface must not be set high before
the switch-on of the V_INT supply of the DDC (I2C) pins, to avoid latch-up of circuits and to permit
a clean boot of the module.
The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires
on the bus increase the capacitance. If the bus capacitance is increased, use pull-up resistors with
nominal resistance value lower than 4.7 k
Ω
, to match the I2C bus specifications
regarding rise and
fall times of the signals.
☞
Capacitance and series resistance must be limited on the bus to match the I2C specifications
(1.0
µ
s is the maximum allowed rise time on the SCL and SDA lines): route connections as short as
possible.
☞
The ESD sensitivity rating of the DDC (I2C) pins is 1 kV (Human Body Model according to
JESD22-A114). A higher protection level could be required if the lines are externally accessible on
the application board. This higher protection level can be achieved by mounting an ESD protection
(e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
☞
If the pins are not used as a DDC bus interface, they can be left unconnected.
