SARA-G450 - System integration manual
UBX-18046432 - R08
Design-in
Page 74 of 143
C1-Public
2.3.2.2
Guidelines for PWR_OFF layout design
The hard power-off circuit (PWR_OFF) requires careful layout due to the pin function: ensure that the
voltage level is well defined during operation and no transient noise is coupled on this line, otherwise
the module might detect a spurious hard power-off request. It is recommended to keep the
connection line to PWR_OFF as short as possible.
2.3.3
Digital I/O interfaces voltage selection (VSEL)
2.3.3.1
Guidelines for VSEL circuit design
The state of VSEL input pin is used to configure the V_INT supply output and the voltage domain for
the generic digital interfaces of the module.
If digital I/O interfaces are intended to operate at 1.8 V, VSEL pin must be connected to GND, as
described in
SARA-G450
21
VSEL
Figure 35: VSEL application circuit, configuring digital interfaces to operate at 1.8 V
If digital I/O interfaces are intended to operate at 3 V, VSEL pin must be left unconnected, as
described in
SARA-G450
21
VSEL
Figure 36: VSEL application circuit, configuring digital interfaces to operate at 3 V
☞
The ESD sensitivity rating of the VSEL pin is 1 kV (Human Body Model according to JESD22-A114).
A higher protection level can be required if the line is externally accessible on the application board.
A higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) close to accessible points.
2.3.3.2
Guidelines for VSEL layout design
There are no specific layout design recommendations for VSEL input.