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UC6226NIS-E310E2 (QFN40) Hardware Reference Design

 

 

 

If the antenna power supply and the chip’s main supply use the same power rail, the ESD, 

surge and overvoltage from the antenna will have an effect on the main supply, which may 

cause damage to the chip. Therefore, it’s recommended to design an independent power 

rail for the antenna to reduce the possibility of damage to the chip. 

2

 

Attention 

2.1

 

Power 

V_DCDC_IN and VDD_IO power supply are independent of each other. There is no strict 

sequence requirement for V_DCDC_IN and VDD_IO, but the lack of any one of them would 

keep  the  chip  in  reset  state. The  rise  time  of V_DCDC_IN  and VDD_IO  when  power  on 

should be less than 10ms and the power supply should be monotonic. After the chip is 

powered on, the start-up time should be more than 230ms, otherwise the chip may work 

abnormally. 

Note: Although the voltage ranges of VDD_IO and V_DCDC_IN / V_CORE have intersection 

and there is no strict sequence requirement, it is still recommended that the two power 

domains be powered independently, because V_DCDC_IN / V_CORE has large current at 

startup and the voltage range of VDD_IO is narrow; if the two domains use the same power 

supply, the instantaneous high current at startup may lead to voltage drop, which may 

pull  down  the  voltage  of  VDD_IO  below  the  working  threshold  and  lead  to  abnormal 

startup. If there are other SoCs on the board that are powered by the same source as the 

UC6226NIS chip, the signal status of the host ports communicating with the chip UART 

needs to be clarified. When the host wants to control the power down of the chip, the ports 

connected with the chip should be set at high resistance state to prevent the chip from 

consuming  the  power  of  the  host  even  after  the  shutdown.  PIO7  and  PIO6  need 

concatenate 1KΩ resistance, if the rest of the PIOs are needed, such as Reset, antenna, 

recommending to concatenate resistance which is at the range of 1KΩ to 4.7KΩ (set the 

resistance value according to the number of ports connected, use 1KΩ for a small number 

of ports, and increase the resistance value appropriately for more ports, the maximum 

value is 4.7KΩ ). 

V_BCKP pin is used for backup power supply, if the application requires to support hot 

start function. It needs to be powered independently. If the application does not require 

hot start, V_BCKP should not be connected to an external power. Instead, it should be 

connected to VDD_IO. 

Summary of Contents for UC6226NIS-E310E2

Page 1: ...HARDWARE REFERENCE DESIGN WWW UNICORECOMM COM Copyright 2009 2023 Unicore Communications Inc Data subject to change without notice UC6226NIS E310E2 QFN40 GNSS Positioning Chip...

Page 2: ...of UNICORECOMM and other trade name trademark icon logo brand name and or service mark of Unicore products or their product serial referred to in this manual collectively Unicore Trademarks This manu...

Page 3: ...onsistent with such information of the specific product you purchase Should you purchase our product and encounter any inconsistency please contact us or our local authorized distributor for the most...

Page 4: ...I Contents 1 Reference Design 1 1 1 Basic Design 1 1 2 Antenna Detection 2 2 Attention 3 2 1 Power 3 2 2 RTC 4 2 3 TCXO 5 3 Recommended BOM 5...

Page 5: ...NA RTC Crystal UART interface It is recommended to use an external independent LDO to power the TCXO The specification of the external power should meet the requirement of the TCXO LNA SAW Main Supply...

Page 6: ...PCB layout the distance between the inductor L5 and the node that connects ANT_IN and the RF line should be as short as possible it is recommended to place one of the metal pads of the L5 inductor on...

Page 7: ...voltage range of VDD_IO is narrow if the two domains use the same power supply the instantaneous high current at startup may lead to voltage drop which may pull down the voltage of VDD_IO below the w...

Page 8: ...an 1 05 V or it may lead to UC6226 getting burned Level requirement for the input signal high level 0 9 V 1 05 V low level 0 V 0 2 V Waveform requirement for the clock duty cycle range should be 45 55...

Page 9: ...al rules 1 It is recommended to maintain copper void for the layer where TCXO is placed and the adjacent layers and keep the reference ground complete for other layers so as to reduce the impact of he...

Page 10: ...Unicore Communications Inc 7 F3 No 7 Fengxian East Road Haidian Beijing P R China 100094 www unicorecomm com Phone 86 10 69939800 Fax 86 10 69939888 info unicorecomm com www unicorecomm com...

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