10.BLOCK DIAGRAM
106
10. BLOCK DIAGRAM
Input Amp.
Gain
coa
rse
ad
j.
Am
p.
Ex
cit
ati
o
n
Refer
ence
10
V
A/D
24
bit
Low
p
ass
filte
r
Zer
o
coar
se ad
j.
Gain
coarse adj.
Para
meter
se
tting
FR
AME
F.
G
+E
XC
+S
-S
-E
XC
-S
IG
+S
IG
Internal Contr
ol
Zer
o
G
ain
Fi
lter
CPU 1
6bi
t
NOV RAM
4
096b
it
External
St
at
us
CJ1
bus contr
ol
LED
Electrically
DC-
DC
DC
5V
IN
+ 8
V
- 8V
E
lectric isolation by photo
-coupler
s
Some of
terminals in
LO
C
K
SW
CPU
unit
F159
inter
nal
CJ1
(
F
rom C
J1 bus
)
C
J1 bus
Iso
lated
vo
ltag
e
volt
age
conver
ter
output
ter
m
ina
l block ar
e used
for
external output
s