Monopolar Control/Display
5-4
Force 2 Service Manual
External Memory
There are eight external memory locations. To ensure accessing only one
peripheral at a time, all external memory locations have addresses with all
bits high except one. The address latch, U9, is continuously active with
addresses on the address/data bus latched with every negative transition
of ALE. When it accesses an external device, it qualifies the latched
address byte with a RD\ or WR\ signal as appropriate, causing the
selected device to be strobed with a negative true read or write signal.
Three of the external memory locations are read only and five are write
only. Previously, the text described one of the write only locations, U8, the
ICM7218C display controller. The following text covers the other seven
locations, starting with the read locations.
Three Read-Only Locations
The three read locations enter the 22 user inputs:
• Fourteen are the keyboard inputs
• Eight are decoded activation inputs.
The signals are grouped logically into activation inputs, mode selection,
and power UP/DOWN control. Tri-state inverting buffers U2, U15, and
U17 gate these signals onto the CPU data bus.
Four Write-Only Locations
There are two 8-bit digital/analog converters (DACs) on the data bus, U21
and U19. These are write only devices. The U21 DAC generates the power
supply control voltage ECON. The U19 DAC generates the RF current
limit analog voltage ICON.
The buffered outputs of the two DACs are further amplified by a gain of
2.4. The final output range of the two analog signals is approximately 0V
to 5V. An LM324 quad op amp, U23, contains all of the amplifiers.
Capacitors C39 and C44 limit RF interference.
If the ECON and ICON signals do not track within a 10% "window," the
Power Alarm circuit on the PSRF board enables an alarm signal; the
generator emits a constant audio tone and disables the RF output. The
REM indicator also comes on. This alarm warns of possible CPU or DAC
problems.
The third write memory location, U6, is a 74LS165 8-bit, parallel-in, serial-
out shift register. this register gates the principal RF clock frequency to
generate the final RF drive envelope.
A 74LS374 octal D-type latch (U4) in the activation circuitry uses the
fourth write location. When the Force 2 is activated, the microcontroller
reads data on the bus. The data identify which device is activate and in
what mode. It then writes this data to latch U4. Two 74LS85 digital
comparators, U7 and U10, compare this stored pattern to the ongoing
activation input. Any change in the activation input will cause the digital
comparators to respond to the difference in inputs and, subsequently, to
Summary of Contents for Force 2-2 PCH
Page 1: ...Service Manual Force 2 Electrosurgical Generator...
Page 10: ...Notes x Force 2 Service Manual...
Page 16: ...Notes 2 4 Force 2 Service Manual...
Page 32: ...Notes 4 10 Force 2 Service Manual...
Page 52: ...Typical Output Waveforms 6 12 Force 2 Service Manual Figure 6 5 Coag 300 Load...
